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[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.

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Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
2006-02-10 00:39:06 +09:00
committed by Ralf Baechle
parent 6307751989
commit 41700e7399
3 changed files with 64 additions and 184 deletions
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include/asm-mips/r4kcache.h
+41 -33
View File
@@ -14,6 +14,7 @@
#include <asm/asm.h>
#include <asm/cacheops.h>
#include <asm/cpu-features.h>
/*
* This macro return a properly sign-extended address suitable as base address
@@ -78,22 +79,25 @@ static inline void flush_scache_line(unsigned long addr)
cache_op(Hit_Writeback_Inv_SD, addr);
}
#define protected_cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3 \n" \
"1: cache %0, (%1) \n" \
"2: .set pop \n" \
" .section __ex_table,\"a\" \n" \
" "STR(PTR)" 1b, 2b \n" \
" .previous" \
: \
: "i" (op), "r" (addr))
/*
* The next two are for badland addresses like signal trampolines.
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set mips3 \n"
"1: cache %0, (%1) \n"
"2: .set pop \n"
" .section __ex_table,\"a\" \n"
" "STR(PTR)" 1b, 2b \n"
" .previous"
:
: "i" (Hit_Invalidate_I), "r" (addr));
protected_cache_op(Hit_Invalidate_I, addr);
}
/*
@@ -104,32 +108,12 @@ static inline void protected_flush_icache_line(unsigned long addr)
*/
static inline void protected_writeback_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set mips3 \n"
"1: cache %0, (%1) \n"
"2: .set pop \n"
" .section __ex_table,\"a\" \n"
" "STR(PTR)" 1b, 2b \n"
" .previous"
:
: "i" (Hit_Writeback_Inv_D), "r" (addr));
protected_cache_op(Hit_Writeback_Inv_D, addr);
}
static inline void protected_writeback_scache_line(unsigned long addr)
{
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set mips3 \n"
"1: cache %0, (%1) \n"
"2: .set pop \n"
" .section __ex_table,\"a\" \n"
" "STR(PTR)" 1b, 2b \n"
" .previous"
:
: "i" (Hit_Writeback_Inv_SD), "r" (addr));
protected_cache_op(Hit_Writeback_Inv_SD, addr);
}
/*
@@ -295,4 +279,28 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
/* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
unsigned long end) \
{ \
unsigned long lsize = cpu_##desc##_line_size(); \
unsigned long addr = start & ~(lsize - 1); \
unsigned long aend = (end - 1) & ~(lsize - 1); \
while (1) { \
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
addr += lsize; \
} \
}
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
/* blast_inv_dcache_range */
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
#endif /* _ASM_R4KCACHE_H */