You've already forked linux-apfs
mirror of
https://github.com/linux-apfs/linux-apfs.git
synced 2026-05-01 15:00:59 -07:00
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -0,0 +1,312 @@
|
||||
/* *********************************************************************
|
||||
* BCM1280/BCM1480 Board Support Package
|
||||
*
|
||||
* Interrupt Mapper definitions File: bcm1480_int.h
|
||||
*
|
||||
* This module contains constants for manipulating the
|
||||
* BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
|
||||
* definitions for the interrupt sources.
|
||||
*
|
||||
* BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _BCM1480_INT_H
|
||||
#define _BCM1480_INT_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/* *********************************************************************
|
||||
* Interrupt Mapper Constants
|
||||
********************************************************************* */
|
||||
|
||||
/*
|
||||
* The interrupt mapper deals with 128-bit logical registers that are
|
||||
* implemented as pairs of 64-bit registers, with the "low" 64 bits in
|
||||
* a register that has an address 0x1000 higher(!) than the
|
||||
* corresponding "high" register.
|
||||
*
|
||||
* For appropriate registers, bit 0 of the "high" register is a
|
||||
* cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
|
||||
* register.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This entire file uses _BCM1480_ in all the symbols because it is
|
||||
* entirely BCM1480 specific.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Interrupt sources (Table 22)
|
||||
*/
|
||||
|
||||
#define K_BCM1480_INT_SOURCES 128
|
||||
|
||||
#define _BCM1480_INT_HIGH(k) (k)
|
||||
#define _BCM1480_INT_LOW(k) ((k)+64)
|
||||
|
||||
#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1)
|
||||
#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4)
|
||||
#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5)
|
||||
#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6)
|
||||
#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7)
|
||||
#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8)
|
||||
#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9)
|
||||
#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10)
|
||||
#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11)
|
||||
#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12)
|
||||
#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13)
|
||||
#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14)
|
||||
#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15)
|
||||
#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20)
|
||||
#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21)
|
||||
#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22)
|
||||
#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23)
|
||||
#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28)
|
||||
#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29)
|
||||
#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30)
|
||||
#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31)
|
||||
#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36)
|
||||
#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37)
|
||||
#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38)
|
||||
#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39)
|
||||
#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40)
|
||||
#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41)
|
||||
#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42)
|
||||
#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43)
|
||||
#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52)
|
||||
#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53)
|
||||
#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54)
|
||||
#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55)
|
||||
#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56)
|
||||
#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57)
|
||||
#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58)
|
||||
#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59)
|
||||
#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60)
|
||||
#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61)
|
||||
#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62)
|
||||
#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63)
|
||||
|
||||
#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1)
|
||||
#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2)
|
||||
#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3)
|
||||
#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4)
|
||||
#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5)
|
||||
#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6)
|
||||
#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7)
|
||||
#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8)
|
||||
#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9)
|
||||
#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10)
|
||||
#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11)
|
||||
#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16)
|
||||
#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17)
|
||||
#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18)
|
||||
#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19)
|
||||
#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20)
|
||||
#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21)
|
||||
#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22)
|
||||
#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23)
|
||||
#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24)
|
||||
#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25)
|
||||
#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32)
|
||||
#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33)
|
||||
#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34)
|
||||
#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35)
|
||||
#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36)
|
||||
#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40)
|
||||
#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41)
|
||||
#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42)
|
||||
#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44)
|
||||
#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45)
|
||||
#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46)
|
||||
#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47)
|
||||
#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52)
|
||||
#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53)
|
||||
#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54)
|
||||
#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55)
|
||||
#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56)
|
||||
#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57)
|
||||
#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58)
|
||||
#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59)
|
||||
#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60)
|
||||
#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61)
|
||||
#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62)
|
||||
#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63)
|
||||
|
||||
/*
|
||||
* Mask values for each interrupt
|
||||
*/
|
||||
|
||||
#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F))
|
||||
#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
|
||||
#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
|
||||
|
||||
#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
|
||||
|
||||
#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
|
||||
#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
|
||||
#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
|
||||
#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
|
||||
#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
|
||||
#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
|
||||
#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
|
||||
#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
|
||||
#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
|
||||
#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
|
||||
#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
|
||||
#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
|
||||
#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
|
||||
#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
|
||||
#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
|
||||
#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
|
||||
#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
|
||||
#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
|
||||
#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
|
||||
#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
|
||||
#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
|
||||
#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
|
||||
#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
|
||||
#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
|
||||
#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
|
||||
#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
|
||||
#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
|
||||
#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
|
||||
#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
|
||||
#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
|
||||
#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
|
||||
#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
|
||||
#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
|
||||
#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
|
||||
#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
|
||||
#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
|
||||
#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
|
||||
#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
|
||||
#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
|
||||
#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
|
||||
#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
|
||||
#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
|
||||
#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
|
||||
#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
|
||||
#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
|
||||
#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
|
||||
#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
|
||||
#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
|
||||
#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
|
||||
#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
|
||||
#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
|
||||
#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
|
||||
#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
|
||||
#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
|
||||
#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
|
||||
#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
|
||||
#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
|
||||
#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
|
||||
#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
|
||||
#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
|
||||
#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
|
||||
#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
|
||||
#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
|
||||
#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
|
||||
#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
|
||||
#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
|
||||
#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
|
||||
#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
|
||||
#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
|
||||
#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
|
||||
#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
|
||||
#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
|
||||
#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
|
||||
#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
|
||||
#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
|
||||
#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
|
||||
#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
|
||||
#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
|
||||
#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
|
||||
#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
|
||||
#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
|
||||
#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
|
||||
#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
|
||||
#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
|
||||
#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
|
||||
#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
|
||||
#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
|
||||
|
||||
/*
|
||||
* Interrupt mappings (Table 18)
|
||||
*/
|
||||
|
||||
#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */
|
||||
#define K_BCM1480_INT_MAP_I1 1
|
||||
#define K_BCM1480_INT_MAP_I2 2
|
||||
#define K_BCM1480_INT_MAP_I3 3
|
||||
#define K_BCM1480_INT_MAP_I4 4
|
||||
#define K_BCM1480_INT_MAP_I5 5
|
||||
#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */
|
||||
#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */
|
||||
|
||||
/*
|
||||
* Interrupt LDT Set Register (Table 19)
|
||||
*/
|
||||
|
||||
#define S_BCM1480_INT_HT_INTMSG 0
|
||||
#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
|
||||
#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
|
||||
#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
|
||||
|
||||
#define K_BCM1480_INT_HT_INTMSG_FIXED 0
|
||||
#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
|
||||
#define K_BCM1480_INT_HT_INTMSG_SMI 2
|
||||
#define K_BCM1480_INT_HT_INTMSG_NMI 3
|
||||
#define K_BCM1480_INT_HT_INTMSG_INIT 4
|
||||
#define K_BCM1480_INT_HT_INTMSG_STARTUP 5
|
||||
#define K_BCM1480_INT_HT_INTMSG_EXTINT 6
|
||||
#define K_BCM1480_INT_HT_INTMSG_RESERVED 7
|
||||
|
||||
#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3)
|
||||
#define V_BCM1480_INT_HT_EDGETRIGGER 0
|
||||
#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE
|
||||
|
||||
#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4)
|
||||
#define V_BCM1480_INT_HT_PHYSICALDEST 0
|
||||
#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
|
||||
|
||||
#define S_BCM1480_INT_HT_INTDEST 5
|
||||
#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
|
||||
#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
|
||||
#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
|
||||
|
||||
#define S_BCM1480_INT_HT_VECTOR 13
|
||||
#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
|
||||
#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
|
||||
#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
|
||||
|
||||
/*
|
||||
* Vector prefix (Table 4-7)
|
||||
*/
|
||||
|
||||
#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00
|
||||
#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40
|
||||
#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80
|
||||
#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0
|
||||
|
||||
#endif /* _BCM1480_INT_H */
|
||||
@@ -0,0 +1,176 @@
|
||||
/* *********************************************************************
|
||||
* BCM1280/BCM1480 Board Support Package
|
||||
*
|
||||
* L2 Cache constants and macros File: bcm1480_l2c.h
|
||||
*
|
||||
* This module contains constants useful for manipulating the
|
||||
* level 2 cache.
|
||||
*
|
||||
* BCM1400 specification level: 1280-UM100-D2 (11/14/03)
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _BCM1480_L2C_H
|
||||
#define _BCM1480_L2C_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/*
|
||||
* Format of level 2 cache management address (Table 55)
|
||||
*/
|
||||
|
||||
#define S_BCM1480_L2C_MGMT_INDEX 5
|
||||
#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
|
||||
#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
|
||||
#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
|
||||
|
||||
#define S_BCM1480_L2C_MGMT_WAY 17
|
||||
#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
|
||||
#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
|
||||
#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
|
||||
|
||||
#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20)
|
||||
#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21)
|
||||
|
||||
#define S_BCM1480_L2C_MGMT_ECC_DIAG 22
|
||||
#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
|
||||
#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
|
||||
#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
|
||||
|
||||
#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000
|
||||
|
||||
#define BCM1480_L2C_ENTRIES_PER_WAY 4096
|
||||
#define BCM1480_L2C_NUM_WAYS 8
|
||||
|
||||
|
||||
/*
|
||||
* Level 2 Cache Tag register (Table 59)
|
||||
*/
|
||||
|
||||
#define S_BCM1480_L2C_TAG_MBZ 0
|
||||
#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
|
||||
|
||||
#define S_BCM1480_L2C_TAG_INDEX 5
|
||||
#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
|
||||
#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
|
||||
#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
|
||||
|
||||
/* Note that index bit 16 is also tag bit 40 */
|
||||
#define S_BCM1480_L2C_TAG_TAG 17
|
||||
#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
|
||||
#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
|
||||
#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
|
||||
|
||||
#define S_BCM1480_L2C_TAG_ECC 40
|
||||
#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
|
||||
#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
|
||||
#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
|
||||
|
||||
#define S_BCM1480_L2C_TAG_WAY 46
|
||||
#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
|
||||
#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
|
||||
#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
|
||||
|
||||
#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49)
|
||||
#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50)
|
||||
|
||||
#define S_BCM1480_L2C_DATA_ECC 51
|
||||
#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
|
||||
#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
|
||||
#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
|
||||
|
||||
|
||||
/*
|
||||
* L2 Misc0 Value Register (Table 60)
|
||||
*/
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0
|
||||
#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
|
||||
#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8
|
||||
#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
|
||||
#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16
|
||||
#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
|
||||
#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24
|
||||
#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
|
||||
#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26
|
||||
#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
|
||||
#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30
|
||||
#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
|
||||
|
||||
#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31
|
||||
#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
|
||||
|
||||
|
||||
/*
|
||||
* L2 Misc1 Value Register (Table 60)
|
||||
*/
|
||||
|
||||
#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0
|
||||
#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
|
||||
#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
|
||||
|
||||
#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8
|
||||
#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
|
||||
#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
|
||||
|
||||
#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16
|
||||
#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
|
||||
#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
|
||||
|
||||
#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24
|
||||
#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
|
||||
#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
|
||||
|
||||
#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32
|
||||
#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
|
||||
#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
|
||||
|
||||
|
||||
/*
|
||||
* L2 Misc2 Value Register (Table 60)
|
||||
*/
|
||||
|
||||
#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0
|
||||
#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
|
||||
#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
|
||||
|
||||
#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8
|
||||
#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
|
||||
#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
|
||||
|
||||
#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16
|
||||
#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
|
||||
#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
|
||||
|
||||
|
||||
#endif /* _BCM1480_L2C_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,406 @@
|
||||
/* *********************************************************************
|
||||
* BCM1280/BCM1400 Board Support Package
|
||||
*
|
||||
* SCD Constants and Macros File: bcm1480_scd.h
|
||||
*
|
||||
* This module contains constants and macros useful for
|
||||
* manipulating the System Control and Debug module.
|
||||
*
|
||||
* BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003,2004,2005
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
#ifndef _BCM1480_SCD_H
|
||||
#define _BCM1480_SCD_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/* *********************************************************************
|
||||
* Pull in the BCM1250's SCD since lots of stuff is the same.
|
||||
********************************************************************* */
|
||||
|
||||
#include "sb1250_scd.h"
|
||||
|
||||
/* *********************************************************************
|
||||
* Some general notes:
|
||||
*
|
||||
* This file is basically a "what's new" header file. Since the
|
||||
* BCM1250 and the new BCM1480 (and derivatives) share many common
|
||||
* features, this file contains only what's new or changed from
|
||||
* the 1250. (above, you can see that we include the 1250 symbols
|
||||
* to get the base functionality).
|
||||
*
|
||||
* In software, be sure to use the correct symbols, particularly
|
||||
* for blocks that are different between the two chip families.
|
||||
* All BCM1480-specific symbols have _BCM1480_ in their names,
|
||||
* and all BCM1250-specific and "base" functions that are common in
|
||||
* both chips have no special names (this is for compatibility with
|
||||
* older include files). Therefore, if you're working with the
|
||||
* SCD, which is very different on each chip, A_SCD_xxx implies
|
||||
* the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
|
||||
* version.
|
||||
********************************************************************* */
|
||||
|
||||
/* *********************************************************************
|
||||
* System control/debug registers
|
||||
********************************************************************* */
|
||||
|
||||
/*
|
||||
* System Identification and Revision Register (Table 12)
|
||||
* Register: SCD_SYSTEM_REVISION
|
||||
* This register is field compatible with the 1250.
|
||||
*/
|
||||
|
||||
/*
|
||||
* New part definitions
|
||||
*/
|
||||
|
||||
#define K_SYS_PART_BCM1480 0x1406
|
||||
#define K_SYS_PART_BCM1280 0x1206
|
||||
#define K_SYS_PART_BCM1455 0x1407
|
||||
#define K_SYS_PART_BCM1255 0x1257
|
||||
#define K_SYS_PART_BCM1158 0x1156
|
||||
|
||||
/*
|
||||
* Manufacturing Information Register (Table 14)
|
||||
* Register: SCD_SYSTEM_MANUF
|
||||
*/
|
||||
|
||||
/*
|
||||
* System Configuration Register (Table 15)
|
||||
* Register: SCD_SYSTEM_CFG
|
||||
* Entire register is different from 1250, all new constants below
|
||||
*/
|
||||
|
||||
#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0)
|
||||
#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1)
|
||||
#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2)
|
||||
#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3)
|
||||
#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4)
|
||||
#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5)
|
||||
|
||||
#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6)
|
||||
#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
|
||||
#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
|
||||
#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
|
||||
|
||||
#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11)
|
||||
#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
|
||||
#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
|
||||
#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
|
||||
|
||||
#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
|
||||
#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17)
|
||||
|
||||
#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18)
|
||||
#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
|
||||
#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
|
||||
#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
|
||||
#define K_BCM1480_SYS_BOOT_MODE_ROM32 0
|
||||
#define K_BCM1480_SYS_BOOT_MODE_ROM8 1
|
||||
#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
|
||||
#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3
|
||||
#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19)
|
||||
|
||||
#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20)
|
||||
#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21)
|
||||
#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
|
||||
#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23)
|
||||
#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24)
|
||||
#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25)
|
||||
|
||||
#define S_BCM1480_SYS_CONFIG 26
|
||||
#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
|
||||
#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
|
||||
#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
|
||||
|
||||
#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15)
|
||||
|
||||
#define S_BCM1480_SYS_NODEID 47
|
||||
#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
|
||||
#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
|
||||
#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
|
||||
|
||||
#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51)
|
||||
#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52)
|
||||
#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53)
|
||||
#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54)
|
||||
#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55)
|
||||
#define S_BCM1480_SYS_DISABLECPU0 56
|
||||
#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
|
||||
#define S_BCM1480_SYS_DISABLECPU1 57
|
||||
#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
|
||||
#define S_BCM1480_SYS_DISABLECPU2 58
|
||||
#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
|
||||
#define S_BCM1480_SYS_DISABLECPU3 59
|
||||
#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
|
||||
|
||||
#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60)
|
||||
#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61)
|
||||
#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62)
|
||||
#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63)
|
||||
|
||||
/*
|
||||
* Scratch Register (Table 16)
|
||||
* Register: SCD_SYSTEM_SCRATCH
|
||||
* Same as BCM1250
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Mailbox Registers (Table 17)
|
||||
* Registers: SCD_MBOX_{0,1}_CPU_x
|
||||
* Same as BCM1250
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* See bcm1480_int.h for interrupt mapper registers.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Watchdog Timer Initial Count Registers (Table 23)
|
||||
* Registers: SCD_WDOG_INIT_CNT_x
|
||||
*
|
||||
* The watchdogs are almost the same as the 1250, except
|
||||
* the configuration register has more bits to control the
|
||||
* other CPUs.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Watchdog Timer Configuration Registers (Table 25)
|
||||
* Registers: SCD_WDOG_CFG_x
|
||||
*/
|
||||
|
||||
#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
|
||||
|
||||
#define S_BCM1480_SCD_WDOG_RESET_TYPE 2
|
||||
#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
|
||||
#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
|
||||
#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
|
||||
|
||||
#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
|
||||
#define K_BCM1480_SCD_WDOG_RESET_SOFT 1
|
||||
#define K_BCM1480_SCD_WDOG_RESET_CPU0 3
|
||||
#define K_BCM1480_SCD_WDOG_RESET_CPU1 5
|
||||
#define K_BCM1480_SCD_WDOG_RESET_CPU2 9
|
||||
#define K_BCM1480_SCD_WDOG_RESET_CPU3 17
|
||||
#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31
|
||||
|
||||
|
||||
#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8)
|
||||
|
||||
/*
|
||||
* General Timer Initial Count Registers (Table 26)
|
||||
* Registers: SCD_TIMER_INIT_x
|
||||
*
|
||||
* The timer registers are the same as the BCM1250
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* ZBbus Count Register (Table 29)
|
||||
* Register: ZBBUS_CYCLE_COUNT
|
||||
*
|
||||
* Same as BCM1250
|
||||
*/
|
||||
|
||||
/*
|
||||
* ZBbus Compare Registers (Table 30)
|
||||
* Registers: ZBBUS_CYCLE_CPx
|
||||
*
|
||||
* Same as BCM1250
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* System Performance Counter Configuration Register (Table 31)
|
||||
* Register: PERF_CNT_CFG_0
|
||||
*
|
||||
* SPC_CFG_SRC[0-3] is the same as the 1250.
|
||||
* SPC_CFG_SRC[4-7] only exist on the 1480
|
||||
* The clear/enable bits are in different locations on the 1250 and 1480.
|
||||
*/
|
||||
|
||||
#define S_SPC_CFG_SRC4 32
|
||||
#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
|
||||
#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
|
||||
#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
|
||||
|
||||
#define S_SPC_CFG_SRC5 40
|
||||
#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
|
||||
#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
|
||||
#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
|
||||
|
||||
#define S_SPC_CFG_SRC6 48
|
||||
#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
|
||||
#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
|
||||
#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
|
||||
|
||||
#define S_SPC_CFG_SRC7 56
|
||||
#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
|
||||
#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
|
||||
#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
|
||||
|
||||
/*
|
||||
* System Performance Counter Control Register (Table 32)
|
||||
* Register: PERF_CNT_CFG_1
|
||||
* BCM1480 specific
|
||||
*/
|
||||
#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
|
||||
#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
|
||||
#if SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR
|
||||
#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* System Performance Counters (Table 33)
|
||||
* Registers: PERF_CNT_x
|
||||
*/
|
||||
|
||||
#define S_BCM1480_SPC_CNT_COUNT 0
|
||||
#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
|
||||
#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
|
||||
#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
|
||||
|
||||
#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40)
|
||||
|
||||
|
||||
/*
|
||||
* Bus Watcher Error Status Register (Tables 36, 37)
|
||||
* Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
|
||||
* Same as BCM1250.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Bus Watcher Error Data Registers (Table 38)
|
||||
* Registers: BUS_ERR_DATA_x
|
||||
* Same as BCM1250.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Bus Watcher L2 ECC Counter Register (Table 39)
|
||||
* Register: BUS_L2_ERRORS
|
||||
* Same as BCM1250.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Bus Watcher Memory and I/O Error Counter Register (Table 40)
|
||||
* Register: BUS_MEM_IO_ERRORS
|
||||
* Same as BCM1250.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Address Trap Registers
|
||||
*
|
||||
* Register layout same as BCM1250, almost. The bus agents
|
||||
* are different, and the address trap configuration bits are
|
||||
* slightly different.
|
||||
*/
|
||||
|
||||
#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0)
|
||||
#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
|
||||
|
||||
#define S_BCM1480_ATRAP_CFG_CNT 0
|
||||
#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
|
||||
#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
|
||||
#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
|
||||
|
||||
#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
|
||||
#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
|
||||
#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5)
|
||||
#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
|
||||
#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
|
||||
|
||||
#define S_BCM1480_ATRAP_CFG_AGENTID 8
|
||||
#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
|
||||
#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
|
||||
#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
|
||||
|
||||
|
||||
#define K_BCM1480_BUS_AGENT_CPU0 0
|
||||
#define K_BCM1480_BUS_AGENT_CPU1 1
|
||||
#define K_BCM1480_BUS_AGENT_NC 2
|
||||
#define K_BCM1480_BUS_AGENT_IOB 3
|
||||
#define K_BCM1480_BUS_AGENT_SCD 4
|
||||
#define K_BCM1480_BUS_AGENT_L2C 6
|
||||
#define K_BCM1480_BUS_AGENT_MC 7
|
||||
#define K_BCM1480_BUS_AGENT_CPU2 8
|
||||
#define K_BCM1480_BUS_AGENT_CPU3 9
|
||||
#define K_BCM1480_BUS_AGENT_PM 10
|
||||
|
||||
#define S_BCM1480_ATRAP_CFG_CATTR 12
|
||||
#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
|
||||
#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
|
||||
#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
|
||||
|
||||
#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0
|
||||
#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1
|
||||
#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2
|
||||
#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3
|
||||
|
||||
#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14)
|
||||
|
||||
|
||||
/*
|
||||
* Trace Event Registers (Table 47)
|
||||
* Same as BCM1250.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Trace Sequence Control Registers (Table 48)
|
||||
* Registers: TRACE_SEQUENCE_x
|
||||
*
|
||||
* Same as BCM1250 except for two new fields.
|
||||
*/
|
||||
|
||||
|
||||
#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25)
|
||||
|
||||
#define S_BCM1480_SCD_TRSEQ_SWFUNC 26
|
||||
#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
|
||||
#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
|
||||
#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
|
||||
|
||||
/*
|
||||
* Trace Control Register (Table 49)
|
||||
* Register: TRACE_CFG
|
||||
*
|
||||
* BCM1480 changes to this register (other than location of the CUR_ADDR field)
|
||||
* are defined below.
|
||||
*/
|
||||
|
||||
#define S_BCM1480_SCD_TRACE_CFG_MODE 16
|
||||
#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
|
||||
#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
|
||||
#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
|
||||
|
||||
#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0
|
||||
#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
|
||||
#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2
|
||||
|
||||
#endif /* _BCM1480_SCD_H */
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
#ifndef __ASM_SIBYTE_BIGSUR_H
|
||||
#define __ASM_SIBYTE_BIGSUR_H
|
||||
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
#include <asm/sibyte/bcm1480_int.h>
|
||||
|
||||
#ifdef CONFIG_SIBYTE_BIGSUR
|
||||
#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
|
||||
#define SIBYTE_HAVE_PCMCIA 1
|
||||
#define SIBYTE_HAVE_IDE 1
|
||||
#endif
|
||||
|
||||
/* Generic bus chip selects */
|
||||
#define LEDS_CS 3
|
||||
#define LEDS_PHYS 0x100a0000
|
||||
|
||||
#ifdef SIBYTE_HAVE_IDE
|
||||
#define IDE_CS 4
|
||||
#define IDE_PHYS 0x100b0000
|
||||
#define K_GPIO_GB_IDE 4
|
||||
#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
|
||||
#endif
|
||||
|
||||
#ifdef SIBYTE_HAVE_PCMCIA
|
||||
#define PCMCIA_CS 6
|
||||
#define PCMCIA_PHYS 0x11000000
|
||||
#define K_GPIO_PC_READY 9
|
||||
#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SIBYTE_BIGSUR_H */
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _SIBYTE_BOARD_H
|
||||
#define _SIBYTE_BOARD_H
|
||||
|
||||
#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
|
||||
defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
|
||||
#include <asm/sibyte/swarm.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
|
||||
#include <asm/sibyte/sentosa.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SIBYTE_CARMEL
|
||||
#include <asm/sibyte/carmel.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SIBYTE_BIGSUR
|
||||
#include <asm/sibyte/bigsur.h>
|
||||
#endif
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#ifdef LEDS_PHYS
|
||||
#define setleds(t0, t1, c0, c1, c2, c3) \
|
||||
li t0, (LEDS_PHYS|0xa0000000); \
|
||||
li t1, c0; \
|
||||
sb t1, 0x18(t0); \
|
||||
li t1, c1; \
|
||||
sb t1, 0x10(t0); \
|
||||
li t1, c2; \
|
||||
sb t1, 0x08(t0); \
|
||||
li t1, c3; \
|
||||
sb t1, 0x00(t0)
|
||||
#else
|
||||
#define setleds(t0, t1, c0, c1, c2, c3)
|
||||
#endif /* LEDS_PHYS */
|
||||
|
||||
#else
|
||||
|
||||
void swarm_setup(void);
|
||||
|
||||
#ifdef LEDS_PHYS
|
||||
extern void setleds(char *str);
|
||||
#else
|
||||
#define setleds(s) do { } while (0)
|
||||
#endif /* LEDS_PHYS */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SIBYTE_BOARD_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (C) 2002 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
#ifndef __ASM_SIBYTE_CARMEL_H
|
||||
#define __ASM_SIBYTE_CARMEL_H
|
||||
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
#include <asm/sibyte/sb1250_int.h>
|
||||
|
||||
#define SIBYTE_BOARD_NAME "Carmel"
|
||||
|
||||
#define GPIO_PHY_INTERRUPT 2
|
||||
#define GPIO_NONMASKABLE_INT 3
|
||||
#define GPIO_CF_INSERTED 6
|
||||
#define GPIO_MONTEREY_RESET 7
|
||||
#define GPIO_QUADUART_INT 8
|
||||
#define GPIO_CF_INT 9
|
||||
#define GPIO_FPGA_CCLK 10
|
||||
#define GPIO_FPGA_DOUT 11
|
||||
#define GPIO_FPGA_DIN 12
|
||||
#define GPIO_FPGA_PGM 13
|
||||
#define GPIO_FPGA_DONE 14
|
||||
#define GPIO_FPGA_INIT 15
|
||||
|
||||
#define LEDS_CS 2
|
||||
#define LEDS_PHYS 0x100C0000
|
||||
#define MLEDS_CS 3
|
||||
#define MLEDS_PHYS 0x100A0000
|
||||
#define UART_CS 4
|
||||
#define UART_PHYS 0x100D0000
|
||||
#define ARAVALI_CS 5
|
||||
#define ARAVALI_PHYS 0x11000000
|
||||
#define IDE_CS 6
|
||||
#define IDE_PHYS 0x100B0000
|
||||
#define ARAVALI2_CS 7
|
||||
#define ARAVALI2_PHYS 0x100E0000
|
||||
|
||||
#if defined(CONFIG_SIBYTE_CARMEL)
|
||||
#define K_GPIO_GB_IDE 9
|
||||
#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __ASM_SIBYTE_CARMEL_H */
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_SIBYTE_SB1250_H
|
||||
#define _ASM_SIBYTE_SB1250_H
|
||||
|
||||
/*
|
||||
* yymmddpp: year, month, day, patch.
|
||||
* should sync with Makefile EXTRAVERSION
|
||||
*/
|
||||
#define SIBYTE_RELEASE 0x02111403
|
||||
|
||||
#define SB1250_NR_IRQS 64
|
||||
|
||||
#define BCM1480_NR_IRQS 128
|
||||
#define BCM1480_NR_IRQS_HALF 64
|
||||
|
||||
#define SB1250_DUART_MINOR_BASE 64
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
/* For revision/pass information */
|
||||
#include <asm/sibyte/sb1250_scd.h>
|
||||
#include <asm/sibyte/bcm1480_scd.h>
|
||||
extern unsigned int sb1_pass;
|
||||
extern unsigned int soc_pass;
|
||||
extern unsigned int soc_type;
|
||||
extern unsigned int periph_rev;
|
||||
extern unsigned int zbbus_mhz;
|
||||
|
||||
extern void sb1250_time_init(void);
|
||||
extern void sb1250_mask_irq(int cpu, int irq);
|
||||
extern void sb1250_unmask_irq(int cpu, int irq);
|
||||
|
||||
extern void bcm1480_time_init(void);
|
||||
extern void bcm1480_mask_irq(int cpu, int irq);
|
||||
extern void bcm1480_unmask_irq(int cpu, int irq);
|
||||
|
||||
#define AT_spin \
|
||||
__asm__ __volatile__ ( \
|
||||
".set noat\n" \
|
||||
"li $at, 0\n" \
|
||||
"1: beqz $at, 1b\n" \
|
||||
".set at\n" \
|
||||
)
|
||||
|
||||
#endif
|
||||
|
||||
#define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,259 @@
|
||||
/* *********************************************************************
|
||||
* SB1250 Board Support Package
|
||||
*
|
||||
* Global constants and macros File: sb1250_defs.h
|
||||
*
|
||||
* This file contains macros and definitions used by the other
|
||||
* include files.
|
||||
*
|
||||
* SB1250 specification level: User's manual 1/02/02
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
#ifndef _SB1250_DEFS_H
|
||||
#define _SB1250_DEFS_H
|
||||
|
||||
/*
|
||||
* These headers require ANSI C89 string concatenation, and GCC or other
|
||||
* 'long long' (64-bit integer) support.
|
||||
*/
|
||||
#if !defined(__STDC__) && !defined(_MSC_VER)
|
||||
#error SiByte headers require ANSI C89 support
|
||||
#endif
|
||||
|
||||
|
||||
/* *********************************************************************
|
||||
* Macros for feature tests, used to enable include file features
|
||||
* for chip features only present in certain chip revisions.
|
||||
*
|
||||
* SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
|
||||
* which is to be exposed by the headers. If undefined, it defaults to
|
||||
* "all features."
|
||||
*
|
||||
* Use like:
|
||||
*
|
||||
* #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1
|
||||
*
|
||||
* Generate defines only for that revision of chip.
|
||||
*
|
||||
* #if SIBYTE_HDR_FEATURE(chip,pass)
|
||||
*
|
||||
* True if header features for that revision or later of
|
||||
* that particular chip type are enabled in SIBYTE_HDR_FEATURES.
|
||||
* (Use this to bracket #defines for features present in a given
|
||||
* revision and later.)
|
||||
*
|
||||
* Note that there is no implied ordering between chip types.
|
||||
*
|
||||
* Note also that 'chip' and 'pass' must textually exactly
|
||||
* match the defines below. So, for example,
|
||||
* SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
|
||||
* SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
|
||||
*
|
||||
* #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
|
||||
*
|
||||
* Same as SIBYTE_HDR_FEATURE, but true for the named revision
|
||||
* and earlier revisions of the named chip type.
|
||||
*
|
||||
* #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
|
||||
*
|
||||
* Same as SIBYTE_HDR_FEATURE, but only true for the named
|
||||
* revision of the named chip type. (Note that this CANNOT
|
||||
* be used to verify that you're compiling only for that
|
||||
* particular chip/revision. It will be true any time this
|
||||
* chip/revision is included in SIBYTE_HDR_FEATURES.)
|
||||
*
|
||||
* #if SIBYTE_HDR_FEATURE_CHIP(chip)
|
||||
*
|
||||
* True if header features for (any revision of) that chip type
|
||||
* are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket
|
||||
* #defines for features specific to a given chip type.)
|
||||
*
|
||||
* Mask values currently include room for additional revisions of each
|
||||
* chip type, but can be renumbered at will. Note that they MUST fit
|
||||
* into 31 bits and may not include C type constructs, for safe use in
|
||||
* CPP conditionals. Bit positions within chip types DO indicate
|
||||
* ordering, so be careful when adding support for new minor revs.
|
||||
********************************************************************* */
|
||||
|
||||
#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff
|
||||
#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001
|
||||
#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002
|
||||
#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004
|
||||
|
||||
#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00
|
||||
#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100
|
||||
|
||||
#define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000
|
||||
#define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000
|
||||
#define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000
|
||||
|
||||
/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
|
||||
#define SIBYTE_HDR_FMASK(chip, pass) \
|
||||
(SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
|
||||
#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
|
||||
(SIBYTE_HDR_FMASK_ ## chip ## _ALL)
|
||||
|
||||
/* Default constant value for all chips, all revisions */
|
||||
#define SIBYTE_HDR_FMASK_ALL \
|
||||
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \
|
||||
| SIBYTE_HDR_FMASK_1480_ALL)
|
||||
|
||||
/* This one is used for the "original" BCM1250/BCM112x chips. We use this
|
||||
to weed out constants and macros that do not exist on later chips like
|
||||
the BCM1480 */
|
||||
#define SIBYTE_HDR_FMASK_1250_112x_ALL \
|
||||
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
|
||||
#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
|
||||
|
||||
#ifndef SIBYTE_HDR_FEATURES
|
||||
#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
|
||||
#endif
|
||||
|
||||
|
||||
/* Bit mask for revisions of chip exclusively before the named revision. */
|
||||
#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \
|
||||
((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
|
||||
|
||||
/* Bit mask for revisions of chip exclusively after the named revision. */
|
||||
#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \
|
||||
(~(SIBYTE_HDR_FMASK(chip, pass) \
|
||||
| (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
|
||||
|
||||
|
||||
/* True if header features enabled for (any revision of) that chip type. */
|
||||
#define SIBYTE_HDR_FEATURE_CHIP(chip) \
|
||||
(!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
|
||||
|
||||
/* True for all versions of the BCM1250 and BCM1125, but not true for
|
||||
anything else */
|
||||
#define SIBYTE_HDR_FEATURE_1250_112x \
|
||||
(SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
|
||||
/* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
|
||||
|
||||
/* True if header features enabled for that rev or later, inclusive. */
|
||||
#define SIBYTE_HDR_FEATURE(chip, pass) \
|
||||
(!! ((SIBYTE_HDR_FMASK(chip, pass) \
|
||||
| SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
|
||||
|
||||
/* True if header features enabled for exactly that rev. */
|
||||
#define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \
|
||||
(!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
|
||||
|
||||
/* True if header features enabled for that rev or before, inclusive. */
|
||||
#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \
|
||||
(!! ((SIBYTE_HDR_FMASK(chip, pass) \
|
||||
| SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
|
||||
|
||||
|
||||
/* *********************************************************************
|
||||
* Naming schemes for constants in these files:
|
||||
*
|
||||
* M_xxx MASK constant (identifies bits in a register).
|
||||
* For multi-bit fields, all bits in the field will
|
||||
* be set.
|
||||
*
|
||||
* K_xxx "Code" constant (value for data in a multi-bit
|
||||
* field). The value is right justified.
|
||||
*
|
||||
* V_xxx "Value" constant. This is the same as the
|
||||
* corresponding "K_xxx" constant, except it is
|
||||
* shifted to the correct position in the register.
|
||||
*
|
||||
* S_xxx SHIFT constant. This is the number of bits that
|
||||
* a field value (code) needs to be shifted
|
||||
* (towards the left) to put the value in the right
|
||||
* position for the register.
|
||||
*
|
||||
* A_xxx ADDRESS constant. This will be a physical
|
||||
* address. Use the PHYS_TO_K1 macro to generate
|
||||
* a K1SEG address.
|
||||
*
|
||||
* R_xxx RELATIVE offset constant. This is an offset from
|
||||
* an A_xxx constant (usually the first register in
|
||||
* a group).
|
||||
*
|
||||
* G_xxx(X) GET value. This macro obtains a multi-bit field
|
||||
* from a register, masks it, and shifts it to
|
||||
* the bottom of the register (retrieving a K_xxx
|
||||
* value, for example).
|
||||
*
|
||||
* V_xxx(X) VALUE. This macro computes the value of a
|
||||
* K_xxx constant shifted to the correct position
|
||||
* in the register.
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Cast to 64-bit number. Presumably the syntax is different in
|
||||
* assembly language.
|
||||
*
|
||||
* Note: you'll need to define uint32_t and uint64_t in your headers.
|
||||
*/
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#define _SB_MAKE64(x) ((uint64_t)(x))
|
||||
#define _SB_MAKE32(x) ((uint32_t)(x))
|
||||
#else
|
||||
#define _SB_MAKE64(x) (x)
|
||||
#define _SB_MAKE32(x) (x)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Make a mask for 1 bit at position 'n'
|
||||
*/
|
||||
|
||||
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
|
||||
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
|
||||
|
||||
/*
|
||||
* Make a mask for 'v' bits at position 'n'
|
||||
*/
|
||||
|
||||
#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
|
||||
#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
|
||||
|
||||
/*
|
||||
* Make a value at 'v' at bit position 'n'
|
||||
*/
|
||||
|
||||
#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
|
||||
#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
|
||||
|
||||
#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
|
||||
#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
|
||||
|
||||
/*
|
||||
* Macros to read/write on-chip registers
|
||||
* XXX should we do the PHYS_TO_K1 here?
|
||||
*/
|
||||
|
||||
|
||||
#if defined(__mips64) && !defined(__ASSEMBLY__)
|
||||
#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
|
||||
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,474 @@
|
||||
/* *********************************************************************
|
||||
* SB1250 Board Support Package
|
||||
*
|
||||
* Generic Bus Constants File: sb1250_genbus.h
|
||||
*
|
||||
* This module contains constants and macros useful for
|
||||
* manipulating the SB1250's Generic Bus interface
|
||||
*
|
||||
* SB1250 specification level: User's manual 10/21/02
|
||||
* BCM1280 specification level: User's Manual 11/14/03
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000, 2001, 2002, 2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _SB1250_GENBUS_H
|
||||
#define _SB1250_GENBUS_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/*
|
||||
* Generic Bus Region Configuration Registers (Table 11-4)
|
||||
*/
|
||||
|
||||
#define S_IO_RDY_ACTIVE 0
|
||||
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
|
||||
|
||||
#define S_IO_ENA_RDY 1
|
||||
#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
|
||||
|
||||
#define S_IO_WIDTH_SEL 2
|
||||
#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
|
||||
#define K_IO_WIDTH_SEL_1 0
|
||||
#define K_IO_WIDTH_SEL_2 1
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|
||||
|| SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define K_IO_WIDTH_SEL_1L 2
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
#define K_IO_WIDTH_SEL_4 3
|
||||
#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
|
||||
#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
|
||||
|
||||
#define S_IO_PARITY_ENA 4
|
||||
#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|
||||
|| SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define S_IO_BURST_EN 5
|
||||
#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
#define S_IO_PARITY_ODD 6
|
||||
#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
|
||||
#define S_IO_NONMUX 7
|
||||
#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
|
||||
|
||||
#define S_IO_TIMEOUT 8
|
||||
#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT)
|
||||
#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT)
|
||||
#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
|
||||
|
||||
/*
|
||||
* Generic Bus Region Size register (Table 11-5)
|
||||
*/
|
||||
|
||||
#define S_IO_MULT_SIZE 0
|
||||
#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE)
|
||||
#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
|
||||
#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
|
||||
|
||||
#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
|
||||
|
||||
/*
|
||||
* Generic Bus Region Address (Table 11-6)
|
||||
*/
|
||||
|
||||
#define S_IO_START_ADDR 0
|
||||
#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR)
|
||||
#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR)
|
||||
#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
|
||||
|
||||
#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
|
||||
|
||||
#define M_IO_BLK_CACHE _SB_MAKEMASK1(15)
|
||||
|
||||
|
||||
/*
|
||||
* Generic Bus Timing 0 Registers (Table 11-7)
|
||||
*/
|
||||
|
||||
#define S_IO_ALE_WIDTH 0
|
||||
#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
|
||||
#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
|
||||
#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|
||||
|| SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#define S_IO_ALE_TO_CS 4
|
||||
#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
|
||||
#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
|
||||
#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|
||||
|| SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define S_IO_BURST_WIDTH _SB_MAKE64(6)
|
||||
#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
|
||||
#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
|
||||
#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#define S_IO_CS_WIDTH 8
|
||||
#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH)
|
||||
#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
|
||||
#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
|
||||
|
||||
#define S_IO_RDY_SMPLE 13
|
||||
#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
|
||||
#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
|
||||
#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
|
||||
|
||||
|
||||
/*
|
||||
* Generic Bus Timing 1 Registers (Table 11-8)
|
||||
*/
|
||||
|
||||
#define S_IO_ALE_TO_WRITE 0
|
||||
#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
|
||||
#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
|
||||
#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|
||||
|| SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#define S_IO_WRITE_WIDTH 4
|
||||
#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
|
||||
#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
|
||||
#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
|
||||
|
||||
#define S_IO_IDLE_CYCLE 8
|
||||
#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
|
||||
#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
|
||||
#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
|
||||
|
||||
#define S_IO_OE_TO_CS 12
|
||||
#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS)
|
||||
#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
|
||||
#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
|
||||
|
||||
#define S_IO_CS_TO_OE 14
|
||||
#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE)
|
||||
#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
|
||||
#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
|
||||
|
||||
/*
|
||||
* Generic Bus Interrupt Status Register (Table 11-9)
|
||||
*/
|
||||
|
||||
#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8)
|
||||
#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
|
||||
#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
|
||||
#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
|
||||
#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
|
||||
#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
|
||||
#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
|
||||
#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
|
||||
#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
|
||||
|
||||
#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
|
||||
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
|
||||
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
|
||||
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define M_IO_COH_ERR _SB_MAKEMASK1(14)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
|
||||
/*
|
||||
* Generic Bus Output Drive Control Register 0 (Table 14-18)
|
||||
*/
|
||||
|
||||
#define S_IO_SLEW0 0
|
||||
#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0)
|
||||
#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0)
|
||||
#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
|
||||
|
||||
#define S_IO_DRV_A 2
|
||||
#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A)
|
||||
#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A)
|
||||
#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
|
||||
|
||||
#define S_IO_DRV_B 6
|
||||
#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B)
|
||||
#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B)
|
||||
#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
|
||||
|
||||
#define S_IO_DRV_C 10
|
||||
#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C)
|
||||
#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C)
|
||||
#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
|
||||
|
||||
#define S_IO_DRV_D 14
|
||||
#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D)
|
||||
#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D)
|
||||
#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
|
||||
|
||||
/*
|
||||
* Generic Bus Output Drive Control Register 1 (Table 14-19)
|
||||
*/
|
||||
|
||||
#define S_IO_DRV_E 2
|
||||
#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E)
|
||||
#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E)
|
||||
#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
|
||||
|
||||
#define S_IO_DRV_F 6
|
||||
#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F)
|
||||
#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F)
|
||||
#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
|
||||
|
||||
#define S_IO_SLEW1 8
|
||||
#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1)
|
||||
#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1)
|
||||
#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
|
||||
|
||||
#define S_IO_DRV_G 10
|
||||
#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G)
|
||||
#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G)
|
||||
#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
|
||||
|
||||
#define S_IO_SLEW2 12
|
||||
#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2)
|
||||
#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2)
|
||||
#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
|
||||
|
||||
#define S_IO_DRV_H 14
|
||||
#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H)
|
||||
#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H)
|
||||
#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
|
||||
|
||||
/*
|
||||
* Generic Bus Output Drive Control Register 2 (Table 14-20)
|
||||
*/
|
||||
|
||||
#define S_IO_DRV_J 2
|
||||
#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J)
|
||||
#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J)
|
||||
#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
|
||||
|
||||
#define S_IO_DRV_K 6
|
||||
#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K)
|
||||
#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K)
|
||||
#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
|
||||
|
||||
#define S_IO_DRV_L 10
|
||||
#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L)
|
||||
#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L)
|
||||
#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
|
||||
|
||||
#define S_IO_DRV_M 14
|
||||
#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M)
|
||||
#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M)
|
||||
#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
|
||||
|
||||
/*
|
||||
* Generic Bus Output Drive Control Register 3 (Table 14-21)
|
||||
*/
|
||||
|
||||
#define S_IO_SLEW3 0
|
||||
#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3)
|
||||
#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3)
|
||||
#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
|
||||
|
||||
#define S_IO_DRV_N 2
|
||||
#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N)
|
||||
#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N)
|
||||
#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
|
||||
|
||||
#define S_IO_DRV_P 6
|
||||
#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P)
|
||||
#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P)
|
||||
#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
|
||||
|
||||
#define S_IO_DRV_Q 10
|
||||
#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q)
|
||||
#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q)
|
||||
#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
|
||||
|
||||
#define S_IO_DRV_R 14
|
||||
#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R)
|
||||
#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R)
|
||||
#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
|
||||
|
||||
|
||||
/*
|
||||
* PCMCIA configuration register (Table 12-6)
|
||||
*/
|
||||
|
||||
#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
|
||||
#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
|
||||
#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
|
||||
#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
|
||||
#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
|
||||
#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
|
||||
#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
|
||||
#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
|
||||
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
|
||||
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define S_PCMCIA_MODE 16
|
||||
#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE)
|
||||
#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE)
|
||||
#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
|
||||
|
||||
#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
|
||||
#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
|
||||
#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */
|
||||
#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */
|
||||
#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */
|
||||
#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */
|
||||
#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* PCMCIA status register (Table 12-7)
|
||||
*/
|
||||
|
||||
#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
|
||||
#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
|
||||
#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
|
||||
#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
|
||||
#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
|
||||
#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
|
||||
#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
|
||||
#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
|
||||
#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
|
||||
#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
|
||||
#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
|
||||
|
||||
/*
|
||||
* GPIO Interrupt Type Register (table 13-3)
|
||||
*/
|
||||
|
||||
#define K_GPIO_INTR_DISABLE 0
|
||||
#define K_GPIO_INTR_EDGE 1
|
||||
#define K_GPIO_INTR_LEVEL 2
|
||||
#define K_GPIO_INTR_SPLIT 3
|
||||
|
||||
#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
|
||||
#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
|
||||
#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
|
||||
#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
|
||||
|
||||
#define S_GPIO_INTR_TYPE0 0
|
||||
#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
|
||||
#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
|
||||
#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
|
||||
|
||||
#define S_GPIO_INTR_TYPE2 2
|
||||
#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
|
||||
#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
|
||||
#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
|
||||
|
||||
#define S_GPIO_INTR_TYPE4 4
|
||||
#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
|
||||
#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
|
||||
#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
|
||||
|
||||
#define S_GPIO_INTR_TYPE6 6
|
||||
#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
|
||||
#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
|
||||
#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
|
||||
|
||||
#define S_GPIO_INTR_TYPE8 8
|
||||
#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
|
||||
#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
|
||||
#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
|
||||
|
||||
#define S_GPIO_INTR_TYPE10 10
|
||||
#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
|
||||
#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
|
||||
#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
|
||||
|
||||
#define S_GPIO_INTR_TYPE12 12
|
||||
#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
|
||||
#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
|
||||
#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
|
||||
|
||||
#define S_GPIO_INTR_TYPE14 14
|
||||
#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
|
||||
#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
|
||||
#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
|
||||
/*
|
||||
* GPIO Interrupt Additional Type Register
|
||||
*/
|
||||
|
||||
#define K_GPIO_INTR_BOTHEDGE 0
|
||||
#define K_GPIO_INTR_RISEEDGE 1
|
||||
#define K_GPIO_INTR_UNPRED1 2
|
||||
#define K_GPIO_INTR_UNPRED2 3
|
||||
|
||||
#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
|
||||
#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
|
||||
#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
|
||||
#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
|
||||
|
||||
#define S_GPIO_INTR_ATYPE0 0
|
||||
#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
|
||||
#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
|
||||
#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE2 2
|
||||
#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
|
||||
#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
|
||||
#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE4 4
|
||||
#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
|
||||
#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
|
||||
#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE6 6
|
||||
#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
|
||||
#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
|
||||
#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE8 8
|
||||
#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
|
||||
#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
|
||||
#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE10 10
|
||||
#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
|
||||
#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
|
||||
#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE12 12
|
||||
#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
|
||||
#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
|
||||
#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
|
||||
|
||||
#define S_GPIO_INTR_ATYPE14 14
|
||||
#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
|
||||
#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
|
||||
#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,248 @@
|
||||
/* *********************************************************************
|
||||
* SB1250 Board Support Package
|
||||
*
|
||||
* Interrupt Mapper definitions File: sb1250_int.h
|
||||
*
|
||||
* This module contains constants for manipulating the SB1250's
|
||||
* interrupt mapper and definitions for the interrupt sources.
|
||||
*
|
||||
* SB1250 specification level: User's manual 1/02/02
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000, 2001, 2002, 2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _SB1250_INT_H
|
||||
#define _SB1250_INT_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/* *********************************************************************
|
||||
* Interrupt Mapper Constants
|
||||
********************************************************************* */
|
||||
|
||||
/*
|
||||
* Interrupt sources (Table 4-8, UM 0.2)
|
||||
*
|
||||
* First, the interrupt numbers.
|
||||
*/
|
||||
|
||||
#define K_INT_SOURCES 64
|
||||
|
||||
#define K_INT_WATCHDOG_TIMER_0 0
|
||||
#define K_INT_WATCHDOG_TIMER_1 1
|
||||
#define K_INT_TIMER_0 2
|
||||
#define K_INT_TIMER_1 3
|
||||
#define K_INT_TIMER_2 4
|
||||
#define K_INT_TIMER_3 5
|
||||
#define K_INT_SMB_0 6
|
||||
#define K_INT_SMB_1 7
|
||||
#define K_INT_UART_0 8
|
||||
#define K_INT_UART_1 9
|
||||
#define K_INT_SER_0 10
|
||||
#define K_INT_SER_1 11
|
||||
#define K_INT_PCMCIA 12
|
||||
#define K_INT_ADDR_TRAP 13
|
||||
#define K_INT_PERF_CNT 14
|
||||
#define K_INT_TRACE_FREEZE 15
|
||||
#define K_INT_BAD_ECC 16
|
||||
#define K_INT_COR_ECC 17
|
||||
#define K_INT_IO_BUS 18
|
||||
#define K_INT_MAC_0 19
|
||||
#define K_INT_MAC_1 20
|
||||
#define K_INT_MAC_2 21
|
||||
#define K_INT_DM_CH_0 22
|
||||
#define K_INT_DM_CH_1 23
|
||||
#define K_INT_DM_CH_2 24
|
||||
#define K_INT_DM_CH_3 25
|
||||
#define K_INT_MBOX_0 26
|
||||
#define K_INT_MBOX_1 27
|
||||
#define K_INT_MBOX_2 28
|
||||
#define K_INT_MBOX_3 29
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define K_INT_CYCLE_CP0_INT 30
|
||||
#define K_INT_CYCLE_CP1_INT 31
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#define K_INT_GPIO_0 32
|
||||
#define K_INT_GPIO_1 33
|
||||
#define K_INT_GPIO_2 34
|
||||
#define K_INT_GPIO_3 35
|
||||
#define K_INT_GPIO_4 36
|
||||
#define K_INT_GPIO_5 37
|
||||
#define K_INT_GPIO_6 38
|
||||
#define K_INT_GPIO_7 39
|
||||
#define K_INT_GPIO_8 40
|
||||
#define K_INT_GPIO_9 41
|
||||
#define K_INT_GPIO_10 42
|
||||
#define K_INT_GPIO_11 43
|
||||
#define K_INT_GPIO_12 44
|
||||
#define K_INT_GPIO_13 45
|
||||
#define K_INT_GPIO_14 46
|
||||
#define K_INT_GPIO_15 47
|
||||
#define K_INT_LDT_FATAL 48
|
||||
#define K_INT_LDT_NONFATAL 49
|
||||
#define K_INT_LDT_SMI 50
|
||||
#define K_INT_LDT_NMI 51
|
||||
#define K_INT_LDT_INIT 52
|
||||
#define K_INT_LDT_STARTUP 53
|
||||
#define K_INT_LDT_EXT 54
|
||||
#define K_INT_PCI_ERROR 55
|
||||
#define K_INT_PCI_INTA 56
|
||||
#define K_INT_PCI_INTB 57
|
||||
#define K_INT_PCI_INTC 58
|
||||
#define K_INT_PCI_INTD 59
|
||||
#define K_INT_SPARE_2 60
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define K_INT_MAC_0_CH1 61
|
||||
#define K_INT_MAC_1_CH1 62
|
||||
#define K_INT_MAC_2_CH1 63
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
|
||||
/*
|
||||
* Mask values for each interrupt
|
||||
*/
|
||||
|
||||
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
|
||||
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
|
||||
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
|
||||
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
|
||||
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
|
||||
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
|
||||
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
|
||||
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
|
||||
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
|
||||
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
|
||||
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
|
||||
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
|
||||
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
|
||||
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
|
||||
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
|
||||
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
|
||||
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
|
||||
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
|
||||
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
|
||||
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
|
||||
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
|
||||
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
|
||||
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
|
||||
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
|
||||
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
|
||||
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
|
||||
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
|
||||
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
|
||||
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
|
||||
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
|
||||
#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
|
||||
#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
|
||||
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
|
||||
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
|
||||
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
|
||||
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
|
||||
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
|
||||
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
|
||||
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
|
||||
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
|
||||
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
|
||||
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
|
||||
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
|
||||
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
|
||||
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
|
||||
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
|
||||
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
|
||||
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
|
||||
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
|
||||
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
|
||||
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
|
||||
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
|
||||
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
|
||||
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
|
||||
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
|
||||
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
|
||||
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
|
||||
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
|
||||
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
|
||||
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
|
||||
#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
|
||||
#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
|
||||
/*
|
||||
* Interrupt mappings
|
||||
*/
|
||||
|
||||
#define K_INT_MAP_I0 0 /* interrupt pins on processor */
|
||||
#define K_INT_MAP_I1 1
|
||||
#define K_INT_MAP_I2 2
|
||||
#define K_INT_MAP_I3 3
|
||||
#define K_INT_MAP_I4 4
|
||||
#define K_INT_MAP_I5 5
|
||||
#define K_INT_MAP_NMI 6 /* nonmaskable */
|
||||
#define K_INT_MAP_DINT 7 /* debug interrupt */
|
||||
|
||||
/*
|
||||
* LDT Interrupt Set Register (table 4-5)
|
||||
*/
|
||||
|
||||
#define S_INT_LDT_INTMSG 0
|
||||
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
|
||||
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
|
||||
#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
|
||||
|
||||
#define K_INT_LDT_INTMSG_FIXED 0
|
||||
#define K_INT_LDT_INTMSG_ARBITRATED 1
|
||||
#define K_INT_LDT_INTMSG_SMI 2
|
||||
#define K_INT_LDT_INTMSG_NMI 3
|
||||
#define K_INT_LDT_INTMSG_INIT 4
|
||||
#define K_INT_LDT_INTMSG_STARTUP 5
|
||||
#define K_INT_LDT_INTMSG_EXTINT 6
|
||||
#define K_INT_LDT_INTMSG_RESERVED 7
|
||||
|
||||
#define M_INT_LDT_EDGETRIGGER 0
|
||||
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
|
||||
|
||||
#define M_INT_LDT_PHYSICALDEST 0
|
||||
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
|
||||
|
||||
#define S_INT_LDT_INTDEST 5
|
||||
#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
|
||||
#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
|
||||
#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
|
||||
|
||||
#define S_INT_LDT_VECTOR 13
|
||||
#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
|
||||
#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
|
||||
#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
|
||||
|
||||
/*
|
||||
* Vector format (Table 4-6)
|
||||
*/
|
||||
|
||||
#define M_LDTVECT_RAISEINT 0x00
|
||||
#define M_LDTVECT_RAISEMBOX 0x40
|
||||
|
||||
|
||||
#endif /* 1250/112x */
|
||||
@@ -0,0 +1,131 @@
|
||||
/* *********************************************************************
|
||||
* SB1250 Board Support Package
|
||||
*
|
||||
* L2 Cache constants and macros File: sb1250_l2c.h
|
||||
*
|
||||
* This module contains constants useful for manipulating the
|
||||
* level 2 cache.
|
||||
*
|
||||
* SB1250 specification level: User's manual 1/02/02
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _SB1250_L2C_H
|
||||
#define _SB1250_L2C_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/*
|
||||
* Level 2 Cache Tag register (Table 5-3)
|
||||
*/
|
||||
|
||||
#define S_L2C_TAG_MBZ 0
|
||||
#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
|
||||
|
||||
#define S_L2C_TAG_INDEX 5
|
||||
#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
|
||||
#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
|
||||
#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
|
||||
|
||||
#define S_L2C_TAG_TAG 17
|
||||
#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG)
|
||||
#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
|
||||
#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
|
||||
|
||||
#define S_L2C_TAG_ECC 40
|
||||
#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC)
|
||||
#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
|
||||
#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
|
||||
|
||||
#define S_L2C_TAG_WAY 46
|
||||
#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY)
|
||||
#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
|
||||
#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
|
||||
|
||||
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
|
||||
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
|
||||
|
||||
/*
|
||||
* Format of level 2 cache management address (table 5-2)
|
||||
*/
|
||||
|
||||
#define S_L2C_MGMT_INDEX 5
|
||||
#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
|
||||
#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
|
||||
#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
|
||||
|
||||
#define S_L2C_MGMT_QUADRANT 15
|
||||
#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
|
||||
#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
|
||||
#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
|
||||
|
||||
#define S_L2C_MGMT_HALF 16
|
||||
#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
|
||||
|
||||
#define S_L2C_MGMT_WAY 17
|
||||
#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
|
||||
#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
|
||||
#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
|
||||
|
||||
#define S_L2C_MGMT_ECC_DIAG 21
|
||||
#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
|
||||
#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
|
||||
#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
|
||||
|
||||
#define S_L2C_MGMT_TAG 23
|
||||
#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
|
||||
#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
|
||||
#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
|
||||
|
||||
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
|
||||
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
|
||||
|
||||
#define A_L2C_MGMT_TAG_BASE 0x00D0000000
|
||||
|
||||
#define L2C_ENTRIES_PER_WAY 4096
|
||||
#define L2C_NUM_WAYS 4
|
||||
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
/*
|
||||
* L2 Read Misc. register (A_L2_READ_MISC)
|
||||
*/
|
||||
#define S_L2C_MISC_NO_WAY 10
|
||||
#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
|
||||
#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
|
||||
#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
|
||||
|
||||
#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
|
||||
#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
|
||||
#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7)
|
||||
#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6)
|
||||
#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5)
|
||||
#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4)
|
||||
#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3)
|
||||
#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2)
|
||||
#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1)
|
||||
#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0)
|
||||
#endif /* 1250 PASS3 || 112x PASS1 */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,423 @@
|
||||
/* *********************************************************************
|
||||
* SB1250 Board Support Package
|
||||
*
|
||||
* LDT constants File: sb1250_ldt.h
|
||||
*
|
||||
* This module contains constants and macros to describe
|
||||
* the LDT interface on the SB1250.
|
||||
*
|
||||
* SB1250 specification level: User's manual 1/02/02
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000, 2001, 2002, 2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _SB1250_LDT_H
|
||||
#define _SB1250_LDT_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
#define K_LDT_VENDOR_SIBYTE 0x166D
|
||||
#define K_LDT_DEVICE_SB1250 0x0002
|
||||
|
||||
/*
|
||||
* LDT Interface Type 1 (bridge) configuration header
|
||||
*/
|
||||
|
||||
#define R_LDT_TYPE1_DEVICEID 0x0000
|
||||
#define R_LDT_TYPE1_CMDSTATUS 0x0004
|
||||
#define R_LDT_TYPE1_CLASSREV 0x0008
|
||||
#define R_LDT_TYPE1_DEVHDR 0x000C
|
||||
#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
|
||||
#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
|
||||
|
||||
#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
|
||||
#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
|
||||
#define R_LDT_TYPE1_MEMLIMIT 0x0020
|
||||
#define R_LDT_TYPE1_PREFETCH 0x0024
|
||||
#define R_LDT_TYPE1_PREF_BASE 0x0028
|
||||
#define R_LDT_TYPE1_PREF_LIMIT 0x002C
|
||||
#define R_LDT_TYPE1_IOLIMIT 0x0030
|
||||
#define R_LDT_TYPE1_CAPPTR 0x0034
|
||||
#define R_LDT_TYPE1_ROMADDR 0x0038
|
||||
#define R_LDT_TYPE1_BRCTL 0x003C
|
||||
#define R_LDT_TYPE1_CMD 0x0040
|
||||
#define R_LDT_TYPE1_LINKCTRL 0x0044
|
||||
#define R_LDT_TYPE1_LINKFREQ 0x0048
|
||||
#define R_LDT_TYPE1_RESERVED1 0x004C
|
||||
#define R_LDT_TYPE1_SRICMD 0x0050
|
||||
#define R_LDT_TYPE1_SRITXNUM 0x0054
|
||||
#define R_LDT_TYPE1_SRIRXNUM 0x0058
|
||||
#define R_LDT_TYPE1_ERRSTATUS 0x0068
|
||||
#define R_LDT_TYPE1_SRICTRL 0x006C
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define R_LDT_TYPE1_ADDSTATUS 0x0070
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#define R_LDT_TYPE1_TXBUFCNT 0x00C8
|
||||
#define R_LDT_TYPE1_EXPCRC 0x00DC
|
||||
#define R_LDT_TYPE1_RXCRC 0x00F0
|
||||
|
||||
|
||||
/*
|
||||
* LDT Device ID register
|
||||
*/
|
||||
|
||||
#define S_LDT_DEVICEID_VENDOR 0
|
||||
#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
|
||||
#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
|
||||
#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
|
||||
|
||||
#define S_LDT_DEVICEID_DEVICEID 16
|
||||
#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
|
||||
#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
|
||||
#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
|
||||
|
||||
|
||||
/*
|
||||
* LDT Command Register (Table 8-13)
|
||||
*/
|
||||
|
||||
#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
|
||||
#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
|
||||
#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
|
||||
#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
|
||||
#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
|
||||
#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
|
||||
#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
|
||||
#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
|
||||
#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
|
||||
#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
|
||||
|
||||
/*
|
||||
* LDT class and revision registers
|
||||
*/
|
||||
|
||||
#define S_LDT_CLASSREV_REV 0
|
||||
#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
|
||||
#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
|
||||
#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
|
||||
|
||||
#define S_LDT_CLASSREV_CLASS 8
|
||||
#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
|
||||
#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
|
||||
#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
|
||||
|
||||
#define K_LDT_REV 0x01
|
||||
#define K_LDT_CLASS 0x060000
|
||||
|
||||
/*
|
||||
* Device Header (offset 0x0C)
|
||||
*/
|
||||
|
||||
#define S_LDT_DEVHDR_CLINESZ 0
|
||||
#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
|
||||
#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
|
||||
#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
|
||||
|
||||
#define S_LDT_DEVHDR_LATTMR 8
|
||||
#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
|
||||
#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
|
||||
#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
|
||||
|
||||
#define S_LDT_DEVHDR_HDRTYPE 16
|
||||
#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
|
||||
#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
|
||||
#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
|
||||
|
||||
#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
|
||||
|
||||
#define S_LDT_DEVHDR_BIST 24
|
||||
#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
|
||||
#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
|
||||
#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* LDT Status Register (Table 8-14). Note that these constants
|
||||
* assume you've read the command and status register
|
||||
* together (32-bit read at offset 0x04)
|
||||
*
|
||||
* These bits also apply to the secondary status
|
||||
* register (Table 8-15), offset 0x1C
|
||||
*/
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
|
||||
#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
|
||||
#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
|
||||
#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
|
||||
#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
|
||||
|
||||
#define S_LDT_STATUS_DEVSELTIMING 25
|
||||
#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
|
||||
#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
|
||||
#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
|
||||
|
||||
#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
|
||||
#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
|
||||
#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
|
||||
#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
|
||||
#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
|
||||
|
||||
/*
|
||||
* Bridge Control Register (Table 8-16). Note that these
|
||||
* constants assume you've read the register as a 32-bit
|
||||
* read (offset 0x3C)
|
||||
*/
|
||||
|
||||
#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
|
||||
#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
|
||||
#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
|
||||
#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
|
||||
#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
|
||||
#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
|
||||
#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
|
||||
#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
|
||||
#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
|
||||
#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
|
||||
#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
|
||||
|
||||
/*
|
||||
* LDT Command Register (Table 8-17). Note that these constants
|
||||
* assume you've read the command and status register together
|
||||
* 32-bit read at offset 0x40
|
||||
*/
|
||||
|
||||
#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
|
||||
#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
|
||||
|
||||
#define S_LDT_CMD_CAPTYPE 29
|
||||
#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
|
||||
#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
|
||||
#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
|
||||
|
||||
/*
|
||||
* LDT link control register (Table 8-18), and (Table 8-19)
|
||||
*/
|
||||
|
||||
#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
|
||||
#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
|
||||
#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
|
||||
#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
|
||||
#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
|
||||
#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
|
||||
#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
|
||||
|
||||
#define S_LDT_LINKCTRL_CRCERR 8
|
||||
#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
|
||||
#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
|
||||
#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
|
||||
|
||||
#define S_LDT_LINKCTRL_MAXIN 16
|
||||
#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
|
||||
#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
|
||||
#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
|
||||
|
||||
#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
|
||||
|
||||
#define S_LDT_LINKCTRL_MAXOUT 20
|
||||
#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
|
||||
#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
|
||||
#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
|
||||
|
||||
#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
|
||||
|
||||
#define S_LDT_LINKCTRL_WIDTHIN 24
|
||||
#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
|
||||
#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
|
||||
#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
|
||||
|
||||
#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
|
||||
|
||||
#define S_LDT_LINKCTRL_WIDTHOUT 28
|
||||
#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
|
||||
#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
|
||||
#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
|
||||
|
||||
#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
|
||||
|
||||
/*
|
||||
* LDT Link frequency register (Table 8-20) offset 0x48
|
||||
*/
|
||||
|
||||
#define S_LDT_LINKFREQ_FREQ 8
|
||||
#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
|
||||
#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
|
||||
#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
|
||||
|
||||
#define K_LDT_LINKFREQ_200MHZ 0
|
||||
#define K_LDT_LINKFREQ_300MHZ 1
|
||||
#define K_LDT_LINKFREQ_400MHZ 2
|
||||
#define K_LDT_LINKFREQ_500MHZ 3
|
||||
#define K_LDT_LINKFREQ_600MHZ 4
|
||||
#define K_LDT_LINKFREQ_800MHZ 5
|
||||
#define K_LDT_LINKFREQ_1000MHZ 6
|
||||
|
||||
/*
|
||||
* LDT SRI Command Register (Table 8-21). Note that these constants
|
||||
* assume you've read the command and status register together
|
||||
* 32-bit read at offset 0x50
|
||||
*/
|
||||
|
||||
#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
|
||||
#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
|
||||
#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
|
||||
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
|
||||
#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */
|
||||
#endif /* up to 1250 PASS1 */
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19)
|
||||
#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
|
||||
|
||||
#define S_LDT_SRICMD_RXMARGIN 20
|
||||
#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
|
||||
#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
|
||||
#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
|
||||
|
||||
#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
|
||||
|
||||
#define S_LDT_SRICMD_TXINITIALOFFSET 28
|
||||
#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
|
||||
#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
|
||||
#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
|
||||
|
||||
#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
|
||||
|
||||
/*
|
||||
* LDT Error control and status register (Table 8-22) (Table 8-23)
|
||||
*/
|
||||
|
||||
#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
|
||||
#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
|
||||
#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
|
||||
#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
|
||||
#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
|
||||
#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
|
||||
#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
|
||||
#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
|
||||
#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
|
||||
#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
|
||||
#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
|
||||
#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
|
||||
#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
|
||||
#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
|
||||
#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
|
||||
#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
|
||||
#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
|
||||
#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
|
||||
|
||||
#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24)
|
||||
#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25)
|
||||
#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26)
|
||||
#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27)
|
||||
#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28)
|
||||
|
||||
/*
|
||||
* SRI Control register (Table 8-24, 8-25) Offset 0x6C
|
||||
*/
|
||||
|
||||
#define S_LDT_SRICTRL_NEEDRESP 0
|
||||
#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
|
||||
#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
|
||||
#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
|
||||
|
||||
#define S_LDT_SRICTRL_NEEDNPREQ 2
|
||||
#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
|
||||
#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
|
||||
#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
|
||||
|
||||
#define S_LDT_SRICTRL_NEEDPREQ 4
|
||||
#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
|
||||
#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
|
||||
#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
|
||||
|
||||
#define S_LDT_SRICTRL_WANTRESP 8
|
||||
#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
|
||||
#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
|
||||
#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
|
||||
|
||||
#define S_LDT_SRICTRL_WANTNPREQ 10
|
||||
#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
|
||||
#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
|
||||
#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
|
||||
|
||||
#define S_LDT_SRICTRL_WANTPREQ 12
|
||||
#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
|
||||
#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
|
||||
#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
|
||||
|
||||
#define S_LDT_SRICTRL_BUFRELSPACE 16
|
||||
#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
|
||||
#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
|
||||
#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
|
||||
|
||||
/*
|
||||
* LDT SRI Transmit Buffer Count register (Table 8-26)
|
||||
*/
|
||||
|
||||
#define S_LDT_TXBUFCNT_PCMD 0
|
||||
#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
|
||||
#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
|
||||
#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
|
||||
|
||||
#define S_LDT_TXBUFCNT_PDATA 4
|
||||
#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
|
||||
#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
|
||||
#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
|
||||
|
||||
#define S_LDT_TXBUFCNT_NPCMD 8
|
||||
#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
|
||||
#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
|
||||
#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
|
||||
|
||||
#define S_LDT_TXBUFCNT_NPDATA 12
|
||||
#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
|
||||
#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
|
||||
#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
|
||||
|
||||
#define S_LDT_TXBUFCNT_RCMD 16
|
||||
#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
|
||||
#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
|
||||
#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
|
||||
|
||||
#define S_LDT_TXBUFCNT_RDATA 20
|
||||
#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
|
||||
#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
|
||||
#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
|
||||
/*
|
||||
* Additional Status Register
|
||||
*/
|
||||
|
||||
#define S_LDT_ADDSTATUS_TGTDONE 0
|
||||
#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
|
||||
#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
|
||||
#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
|
||||
#endif /* 1250 PASS2 || 112x PASS1 */
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,204 @@
|
||||
/* *********************************************************************
|
||||
* SB1250 Board Support Package
|
||||
*
|
||||
* SMBUS Constants File: sb1250_smbus.h
|
||||
*
|
||||
* This module contains constants and macros useful for
|
||||
* manipulating the SB1250's SMbus devices.
|
||||
*
|
||||
* SB1250 specification level: 10/21/02
|
||||
* BCM1280 specification level: 11/24/03
|
||||
*
|
||||
*********************************************************************
|
||||
*
|
||||
* Copyright 2000,2001,2002,2003
|
||||
* Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
#ifndef _SB1250_SMBUS_H
|
||||
#define _SB1250_SMBUS_H
|
||||
|
||||
#include "sb1250_defs.h"
|
||||
|
||||
/*
|
||||
* SMBus Clock Frequency Register (Table 14-2)
|
||||
*/
|
||||
|
||||
#define S_SMB_FREQ_DIV 0
|
||||
#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
|
||||
#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
|
||||
|
||||
#define K_SMB_FREQ_400KHZ 0x1F
|
||||
#define K_SMB_FREQ_100KHZ 0x7D
|
||||
#define K_SMB_FREQ_10KHZ 1250
|
||||
|
||||
#define S_SMB_CMD 0
|
||||
#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD)
|
||||
#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD)
|
||||
|
||||
/*
|
||||
* SMBus control register (Table 14-4)
|
||||
*/
|
||||
|
||||
#define M_SMB_ERR_INTR _SB_MAKEMASK1(0)
|
||||
#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1)
|
||||
|
||||
#define S_SMB_DATA_OUT 4
|
||||
#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
|
||||
#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
|
||||
|
||||
#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
|
||||
#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
|
||||
#define M_SMB_CLK_OUT _SB_MAKEMASK1(6)
|
||||
#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7)
|
||||
|
||||
/*
|
||||
* SMBus status registers (Table 14-5)
|
||||
*/
|
||||
|
||||
#define M_SMB_BUSY _SB_MAKEMASK1(0)
|
||||
#define M_SMB_ERROR _SB_MAKEMASK1(1)
|
||||
#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2)
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
#define S_SMB_SCL_IN 5
|
||||
#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
|
||||
#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN)
|
||||
#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
|
||||
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
|
||||
|
||||
#define S_SMB_REF 6
|
||||
#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
|
||||
#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF)
|
||||
#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
|
||||
|
||||
#define S_SMB_DATA_IN 7
|
||||
#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
|
||||
#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN)
|
||||
#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
|
||||
|
||||
/*
|
||||
* SMBus Start/Command registers (Table 14-9)
|
||||
*/
|
||||
|
||||
#define S_SMB_ADDR 0
|
||||
#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR)
|
||||
#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR)
|
||||
#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
|
||||
|
||||
#define M_SMB_QDATA _SB_MAKEMASK1(7)
|
||||
|
||||
#define S_SMB_TT 8
|
||||
#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT)
|
||||
#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT)
|
||||
#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
|
||||
|
||||
#define K_SMB_TT_WR1BYTE 0
|
||||
#define K_SMB_TT_WR2BYTE 1
|
||||
#define K_SMB_TT_WR3BYTE 2
|
||||
#define K_SMB_TT_CMD_RD1BYTE 3
|
||||
#define K_SMB_TT_CMD_RD2BYTE 4
|
||||
#define K_SMB_TT_RD1BYTE 5
|
||||
#define K_SMB_TT_QUICKCMD 6
|
||||
#define K_SMB_TT_EEPROMREAD 7
|
||||
|
||||
#define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE)
|
||||
#define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE)
|
||||
#define V_SMB_TT_WR3BYTE V_SMB_TT(K_SMB_TT_WR3BYTE)
|
||||
#define V_SMB_TT_CMD_RD1BYTE V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
|
||||
#define V_SMB_TT_CMD_RD2BYTE V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
|
||||
#define V_SMB_TT_RD1BYTE V_SMB_TT(K_SMB_TT_RD1BYTE)
|
||||
#define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD)
|
||||
#define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD)
|
||||
|
||||
#define M_SMB_PEC _SB_MAKEMASK1(15)
|
||||
|
||||
/*
|
||||
* SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
|
||||
*/
|
||||
|
||||
#define S_SMB_LB 0
|
||||
#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB)
|
||||
#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB)
|
||||
|
||||
#define S_SMB_MB 8
|
||||
#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB)
|
||||
#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB)
|
||||
|
||||
|
||||
/*
|
||||
* SMBus Packet Error Check register (Table 14-8)
|
||||
*/
|
||||
|
||||
#define S_SPEC_PEC 0
|
||||
#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC)
|
||||
#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC)
|
||||
|
||||
|
||||
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
|
||||
|
||||
#define S_SMB_CMDH 8
|
||||
#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH)
|
||||
#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH)
|
||||
|
||||
#define M_SMB_EXTEND _SB_MAKEMASK1(14)
|
||||
|
||||
#define S_SMB_DFMT 8
|
||||
#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT)
|
||||
#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT)
|
||||
#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
|
||||
|
||||
#define K_SMB_DFMT_1BYTE 0
|
||||
#define K_SMB_DFMT_2BYTE 1
|
||||
#define K_SMB_DFMT_3BYTE 2
|
||||
#define K_SMB_DFMT_4BYTE 3
|
||||
#define K_SMB_DFMT_NODATA 4
|
||||
#define K_SMB_DFMT_CMD4BYTE 5
|
||||
#define K_SMB_DFMT_CMD5BYTE 6
|
||||
#define K_SMB_DFMT_RESERVED 7
|
||||
|
||||
#define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE)
|
||||
#define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE)
|
||||
#define V_SMB_DFMT_3BYTE V_SMB_DFMT(K_SMB_DFMT_3BYTE)
|
||||
#define V_SMB_DFMT_4BYTE V_SMB_DFMT(K_SMB_DFMT_4BYTE)
|
||||
#define V_SMB_DFMT_NODATA V_SMB_DFMT(K_SMB_DFMT_NODATA)
|
||||
#define V_SMB_DFMT_CMD4BYTE V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
|
||||
#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
|
||||
#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
|
||||
|
||||
#define S_SMB_AFMT 11
|
||||
#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT)
|
||||
#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT)
|
||||
#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
|
||||
|
||||
#define K_SMB_AFMT_NONE 0
|
||||
#define K_SMB_AFMT_ADDR 1
|
||||
#define K_SMB_AFMT_ADDR_CMD1BYTE 2
|
||||
#define K_SMB_AFMT_ADDR_CMD2BYTE 3
|
||||
|
||||
#define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE)
|
||||
#define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR)
|
||||
#define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
|
||||
#define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
|
||||
|
||||
#define M_SMB_DIR _SB_MAKEMASK1(13)
|
||||
|
||||
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user