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drm/i915: Give names to more ring registers

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The logical render context population has a bunch of raw ring register
offsets. Use the names we have for them, and in cases where we we don't,
give them names.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-23-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Ville Syrjälä
2015-11-04 23:20:10 +02:00
parent 9244a81701
commit 35dc3f97a6
2 changed files with 19 additions and 11 deletions
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drivers/gpu/drm/i915/i915_reg.h
+8
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@@ -1653,8 +1653,16 @@ enum skl_disp_power_wells {
#define HWSTAM 0x02098
#define DMA_FADD_I8XX 0x020d0
#define RING_BBSTATE(base) ((base)+0x110)
#define RING_BB_PPGTT (1 << 5)
#define RING_SBBADDR(base) ((base)+0x114) /* hsw+ */
#define RING_SBBSTATE(base) ((base)+0x118) /* hsw+ */
#define RING_SBBADDR_UDW(base) ((base)+0x11c) /* gen8+ */
#define RING_BBADDR(base) ((base)+0x140)
#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
#define RING_BB_PER_CTX_PTR(base) ((base)+0x1c0) /* gen8+ */
#define RING_INDIRECT_CTX(base) ((base)+0x1c4) /* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base) ((base)+0x1c8) /* gen8+ */
#define RING_CTX_TIMESTAMP(base) ((base)+0x3a8) /* gen8+ */
#define ERROR_GEN6 0x040a0
#define GEN7_ERR_INT 0x44040