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Merge branch 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

Browse Source 
Rather large pull request this time around, due to the long-pending
cleanup of the kernel driver being here.  There's a stupidly large
number of commits for that, as I wanted to have the series be
bisectable at a fairly fine-grained level.  That said, a very large
portion of the churn in the rework was automated, and a very large
number of boards from right across the whole range we support have
been tested.  I'm fairly confident there shouldn't be (too many)
issues from this.

Beyond correcting some not-so-great design decisions and making the
code a lot easier to work with, there's not much exciting (lower
memory usage, GPU VM should be a lot faster, etc) to be gained by the
end-user as a result of the cleanup, it mostly lays the groundwork for
future improvements.

A big thanks goes to Alexandre Courbot for testing/debugging the GK20A
codepaths for me :)

Highlights:
- A heap of perfmon work, providing a more useful userspace interface
and specifying counters for a bunch of boards
- Support for GT200 reclocking + other misc pm improvements
- Initial patches towards supporting GM20B (Tegra X1)
- Maxwell DisplayPort fixes
- Cleanup of the kernel driver
- The usual collection of random fixes

* 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (312 commits)
  drm/nouveau: bump driver version for release
  drm/nouveau/tegra: merge platform setup from nouveau drm
  drm/nouveau/pci: merge agp handling from nouveau drm
  drm/nouveau/device: remove pci/platform_device from common struct
  drm/nouveau/device: import pciid list and integrate quirks with it
  drm/nouveau/device: cleaner abstraction for device resource functions
  drm/nouveau/mc: move device irq handling to platform-specific code
  drm/nouveau/mc/gf100-: handle second interrupt tree
  drm/nouveau/mc: abstract interface to master intr registers
  drm/nouveau/pci: new subdev
  drm/nouveau/object: merge with handle
  drm/nouveau/core: remove the remainder of the previous style
  drm/nouveau/mpeg: convert to new-style nvkm_engine
  drm/nouveau/sw: convert to new-style nvkm_engine
  drm/nouveau/pm: convert to new-style nvkm_engine
  drm/nouveau/gr: convert to new-style nvkm_engine
  drm/nouveau/fifo: convert to new-style nvkm_engine
  drm/nouveau/disp: convert to new-style nvkm_engine
  drm/nouveau/dma: convert to new-style nvkm_engine
  drm/nouveau/cipher: convert to new-style nvkm_engine
  ...
This commit is contained in:
Dave Airlie
2015-08-28 13:20:09 +10:00
parent d7b273685f a3c1ff87cf
commit 3439633a85
728 changed files with 43490 additions and 38358 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/nouveau/Kbuild
-1
View File
@@ -18,7 +18,6 @@ nouveau-y += $(nvkm-y)
ifdef CONFIG_X86 ifdef CONFIG_X86
nouveau-$(CONFIG_ACPI) += nouveau_acpi.o nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
endif endif
nouveau-y += nouveau_agp.o
nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o
nouveau-y += nouveau_drm.o nouveau-y += nouveau_drm.o
nouveau-y += nouveau_hwmon.o nouveau-y += nouveau_hwmon.o
drivers/gpu/drm/nouveau/dispnv04/arb.c
+1 -1
View File
@@ -198,7 +198,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
int *burst, int *lwm) int *burst, int *lwm)
{ {
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nv_fifo_info fifo_data; struct nv_fifo_info fifo_data;
struct nv_sim_state sim_data; struct nv_sim_state sim_data;
int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
drivers/gpu/drm/nouveau/dispnv04/dac.c
+25 -20
View File
@@ -65,8 +65,8 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
static int sample_load_twice(struct drm_device *dev, bool sense[2]) static int sample_load_twice(struct drm_device *dev, bool sense[2])
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_timer *ptimer = nvxx_timer(device); struct nvif_object *device = &drm->device.object;
int i; int i;
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
@@ -80,17 +80,22 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])
* use a 10ms timeout (guards against crtc being inactive, in * use a 10ms timeout (guards against crtc being inactive, in
* which case blank state would never change) * which case blank state would never change)
*/ */
if (!nvkm_timer_wait_eq(ptimer, 10000000, if (nvif_msec(&drm->device, 10,
NV_PRMCIO_INP0__COLOR, if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
0x00000001, 0x00000000)) break;
) < 0)
return -EBUSY; return -EBUSY;
if (!nvkm_timer_wait_eq(ptimer, 10000000,
NV_PRMCIO_INP0__COLOR, if (nvif_msec(&drm->device, 10,
0x00000001, 0x00000001)) if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
break;
) < 0)
return -EBUSY; return -EBUSY;
if (!nvkm_timer_wait_eq(ptimer, 10000000,
NV_PRMCIO_INP0__COLOR, if (nvif_msec(&drm->device, 10,
0x00000001, 0x00000000)) if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1))
break;
) < 0)
return -EBUSY; return -EBUSY;
udelay(100); udelay(100);
@@ -128,7 +133,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
struct drm_connector *connector) struct drm_connector *connector)
{ {
struct drm_device *dev = encoder->dev; struct drm_device *dev = encoder->dev;
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode; uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
uint8_t saved_palette0[3], saved_palette_mask; uint8_t saved_palette0[3], saved_palette_mask;
@@ -231,8 +236,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
{ {
struct drm_device *dev = encoder->dev; struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nvkm_gpio *gpio = nvxx_gpio(device); struct nvkm_gpio *gpio = nvxx_gpio(&drm->device);
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
@@ -265,10 +270,10 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
} }
if (gpio) { if (gpio) {
saved_gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff); saved_gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
saved_gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff); saved_gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, dcb->type == DCB_OUTPUT_TV); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, dcb->type == DCB_OUTPUT_TV);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, dcb->type == DCB_OUTPUT_TV); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, dcb->type == DCB_OUTPUT_TV);
} }
msleep(4); msleep(4);
@@ -320,8 +325,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
if (gpio) { if (gpio) {
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, saved_gpio0); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, saved_gpio0);
} }
return sample; return sample;
drivers/gpu/drm/nouveau/dispnv04/dfp.c
+10 -11
View File
@@ -281,7 +281,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode) struct drm_display_mode *adjusted_mode)
{ {
struct drm_device *dev = encoder->dev; struct drm_device *dev = encoder->dev;
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
@@ -493,11 +493,11 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 || if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) { dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
if (mode == DRM_MODE_DPMS_ON) { if (mode == DRM_MODE_DPMS_ON) {
nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31); nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1); nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
} else { } else {
nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0); nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0); nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
} }
} }
#endif #endif
@@ -624,8 +624,8 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nvkm_i2c_port *port = i2c->find(i2c, 2); struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI);
struct nvkm_i2c_board_info info[] = { struct nvkm_i2c_bus_probe info[] = {
{ {
{ {
.type = "sil164", .type = "sil164",
@@ -639,16 +639,15 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
}; };
int type; int type;
if (!nv_gf4_disp_arch(dev) || !port || if (!nv_gf4_disp_arch(dev) || !bus || get_tmds_slave(encoder))
get_tmds_slave(encoder))
return; return;
type = i2c->identify(i2c, 2, "TMDS transmitter", info, NULL, NULL); type = nvkm_i2c_bus_probe(bus, "TMDS transmitter", info, NULL, NULL);
if (type < 0) if (type < 0)
return; return;
drm_i2c_encoder_init(dev, to_encoder_slave(encoder), drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
&port->adapter, &info[type].dev); &bus->i2c, &info[type].dev);
} }
static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = { static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
drivers/gpu/drm/nouveau/dispnv04/disp.c
+5 -3
View File
@@ -47,7 +47,7 @@ nv04_display_create(struct drm_device *dev)
if (!disp) if (!disp)
return -ENOMEM; return -ENOMEM;
nvif_object_map(nvif_object(&drm->device)); nvif_object_map(&drm->device.object);
nouveau_display(dev)->priv = disp; nouveau_display(dev)->priv = disp;
nouveau_display(dev)->dtor = nv04_display_destroy; nouveau_display(dev)->dtor = nv04_display_destroy;
@@ -101,7 +101,9 @@ nv04_display_create(struct drm_device *dev)
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
nv_encoder->i2c = i2c->find(i2c, nv_encoder->dcb->i2c_index); struct nvkm_i2c_bus *bus =
nvkm_i2c_bus_find(i2c, nv_encoder->dcb->i2c_index);
nv_encoder->i2c = bus ? &bus->i2c : NULL;
} }
/* Save previous state */ /* Save previous state */
@@ -151,7 +153,7 @@ nv04_display_destroy(struct drm_device *dev)
nouveau_display(dev)->priv = NULL; nouveau_display(dev)->priv = NULL;
kfree(disp); kfree(disp);
nvif_object_unmap(nvif_object(&drm->device)); nvif_object_unmap(&drm->device.object);
} }
int int
drivers/gpu/drm/nouveau/dispnv04/disp.h
+1 -1
View File
@@ -172,7 +172,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_bios *bios = nvxx_bios(&drm->device); struct nvkm_bios *bios = nvxx_bios(&drm->device);
struct nvbios_init init = { struct nvbios_init init = {
.subdev = nv_subdev(bios), .subdev = &bios->subdev,
.bios = bios, .bios = bios,
.offset = table, .offset = table,
.outp = outp, .outp = outp,
drivers/gpu/drm/nouveau/dispnv04/hw.c
+17 -12
View File
@@ -165,8 +165,8 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
struct nvkm_pll_vals *pllvals) struct nvkm_pll_vals *pllvals)
{ {
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device; struct nvif_object *device = &drm->device.object;
struct nvkm_bios *bios = nvxx_bios(device); struct nvkm_bios *bios = nvxx_bios(&drm->device);
uint32_t reg1, pll1, pll2 = 0; uint32_t reg1, pll1, pll2 = 0;
struct nvbios_pll pll_lim; struct nvbios_pll pll_lim;
int ret; int ret;
@@ -660,8 +660,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
struct nv04_mode_state *state) struct nv04_mode_state *state)
{ {
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device; struct nvif_object *device = &drm->device.object;
struct nvkm_timer *ptimer = nvxx_timer(device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head]; struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t reg900; uint32_t reg900;
int i; int i;
@@ -678,10 +677,10 @@ nv_load_state_ext(struct drm_device *dev, int head,
nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
nvif_wr32(device, NV_PVIDEO_LIMIT(0), device->info.ram_size - 1); nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_LIMIT(1), device->info.ram_size - 1); nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), device->info.ram_size - 1); nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), device->info.ram_size - 1); nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->device.info.ram_size - 1);
nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
@@ -741,8 +740,14 @@ nv_load_state_ext(struct drm_device *dev, int head,
if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
/* Not waiting for vertical retrace before modifying /* Not waiting for vertical retrace before modifying
CRE_53/CRE_54 causes lockups. */ CRE_53/CRE_54 causes lockups. */
nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); nvif_msec(&drm->device, 650,
nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
break;
);
nvif_msec(&drm->device, 650,
if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
break;
);
} }
wr_cio_state(dev, head, regp, NV_CIO_CRE_42); wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
@@ -765,7 +770,7 @@ static void
nv_save_state_palette(struct drm_device *dev, int head, nv_save_state_palette(struct drm_device *dev, int head,
struct nv04_mode_state *state) struct nv04_mode_state *state)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
int head_offset = head * NV_PRMDIO_SIZE, i; int head_offset = head * NV_PRMDIO_SIZE, i;
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
@@ -784,7 +789,7 @@ void
nouveau_hw_load_state_palette(struct drm_device *dev, int head, nouveau_hw_load_state_palette(struct drm_device *dev, int head,
struct nv04_mode_state *state) struct nv04_mode_state *state)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
int head_offset = head * NV_PRMDIO_SIZE, i; int head_offset = head * NV_PRMDIO_SIZE, i;
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
drivers/gpu/drm/nouveau/dispnv04/hw.h
+13 -13
View File
@@ -60,7 +60,7 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
static inline uint32_t NVReadCRTC(struct drm_device *dev, static inline uint32_t NVReadCRTC(struct drm_device *dev,
int head, uint32_t reg) int head, uint32_t reg)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint32_t val; uint32_t val;
if (head) if (head)
reg += NV_PCRTC0_SIZE; reg += NV_PCRTC0_SIZE;
@@ -71,7 +71,7 @@ static inline uint32_t NVReadCRTC(struct drm_device *dev,
static inline void NVWriteCRTC(struct drm_device *dev, static inline void NVWriteCRTC(struct drm_device *dev,
int head, uint32_t reg, uint32_t val) int head, uint32_t reg, uint32_t val)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
if (head) if (head)
reg += NV_PCRTC0_SIZE; reg += NV_PCRTC0_SIZE;
nvif_wr32(device, reg, val); nvif_wr32(device, reg, val);
@@ -80,7 +80,7 @@ static inline void NVWriteCRTC(struct drm_device *dev,
static inline uint32_t NVReadRAMDAC(struct drm_device *dev, static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
int head, uint32_t reg) int head, uint32_t reg)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint32_t val; uint32_t val;
if (head) if (head)
reg += NV_PRAMDAC0_SIZE; reg += NV_PRAMDAC0_SIZE;
@@ -91,7 +91,7 @@ static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
static inline void NVWriteRAMDAC(struct drm_device *dev, static inline void NVWriteRAMDAC(struct drm_device *dev,
int head, uint32_t reg, uint32_t val) int head, uint32_t reg, uint32_t val)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
if (head) if (head)
reg += NV_PRAMDAC0_SIZE; reg += NV_PRAMDAC0_SIZE;
nvif_wr32(device, reg, val); nvif_wr32(device, reg, val);
@@ -120,7 +120,7 @@ static inline void nv_write_tmds(struct drm_device *dev,
static inline void NVWriteVgaCrtc(struct drm_device *dev, static inline void NVWriteVgaCrtc(struct drm_device *dev,
int head, uint8_t index, uint8_t value) int head, uint8_t index, uint8_t value)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value); nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
} }
@@ -128,7 +128,7 @@ static inline void NVWriteVgaCrtc(struct drm_device *dev,
static inline uint8_t NVReadVgaCrtc(struct drm_device *dev, static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
int head, uint8_t index) int head, uint8_t index)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint8_t val; uint8_t val;
nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
@@ -165,7 +165,7 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_
static inline uint8_t NVReadPRMVIO(struct drm_device *dev, static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
int head, uint32_t reg) int head, uint32_t reg)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
uint8_t val; uint8_t val;
@@ -181,7 +181,7 @@ static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
static inline void NVWritePRMVIO(struct drm_device *dev, static inline void NVWritePRMVIO(struct drm_device *dev,
int head, uint32_t reg, uint8_t value) int head, uint32_t reg, uint8_t value)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
/* Only NV4x have two pvio ranges; other twoHeads cards MUST call /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
@@ -194,14 +194,14 @@ static inline void NVWritePRMVIO(struct drm_device *dev,
static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable) static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
} }
static inline bool NVGetEnablePalette(struct drm_device *dev, int head) static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
} }
@@ -209,7 +209,7 @@ static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
static inline void NVWriteVgaAttr(struct drm_device *dev, static inline void NVWriteVgaAttr(struct drm_device *dev,
int head, uint8_t index, uint8_t value) int head, uint8_t index, uint8_t value)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
if (NVGetEnablePalette(dev, head)) if (NVGetEnablePalette(dev, head))
index &= ~0x20; index &= ~0x20;
else else
@@ -223,7 +223,7 @@ static inline void NVWriteVgaAttr(struct drm_device *dev,
static inline uint8_t NVReadVgaAttr(struct drm_device *dev, static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
int head, uint8_t index) int head, uint8_t index)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
uint8_t val; uint8_t val;
if (NVGetEnablePalette(dev, head)) if (NVGetEnablePalette(dev, head))
index &= ~0x20; index &= ~0x20;
@@ -259,7 +259,7 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
static inline bool static inline bool
nv_heads_tied(struct drm_device *dev) nv_heads_tied(struct drm_device *dev)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_object *device = &nouveau_drm(dev)->device.object;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
if (drm->device.info.chipset == 0x11) if (drm->device.info.chipset == 0x11)
drivers/gpu/drm/nouveau/dispnv04/overlay.c
+7 -6
View File
@@ -96,7 +96,8 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y, uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h) uint32_t src_w, uint32_t src_h)
{ {
struct nvif_device *dev = &nouveau_drm(plane->dev)->device; struct nouveau_drm *drm = nouveau_drm(plane->dev);
struct nvif_object *dev = &drm->device.object;
struct nouveau_plane *nv_plane = struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base); container_of(plane, struct nouveau_plane, base);
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
@@ -118,7 +119,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
if (format > 0xffff) if (format > 0xffff)
return -ERANGE; return -ERANGE;
if (dev->info.chipset >= 0x30) { if (drm->device.info.chipset >= 0x30) {
if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))
return -ERANGE; return -ERANGE;
} else { } else {
@@ -173,7 +174,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
static int static int
nv10_disable_plane(struct drm_plane *plane) nv10_disable_plane(struct drm_plane *plane)
{ {
struct nvif_device *dev = &nouveau_drm(plane->dev)->device; struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object;
struct nouveau_plane *nv_plane = struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base); container_of(plane, struct nouveau_plane, base);
@@ -197,7 +198,7 @@ nv_destroy_plane(struct drm_plane *plane)
static void static void
nv10_set_params(struct nouveau_plane *plane) nv10_set_params(struct nouveau_plane *plane)
{ {
struct nvif_device *dev = &nouveau_drm(plane->base.dev)->device; struct nvif_object *dev = &nouveau_drm(plane->base.dev)->device.object;
u32 luma = (plane->brightness - 512) << 16 | plane->contrast; u32 luma = (plane->brightness - 512) << 16 | plane->contrast;
u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) | u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) |
(cos_mul(plane->hue, plane->saturation) & 0xffff); (cos_mul(plane->hue, plane->saturation) & 0xffff);
@@ -346,7 +347,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y, uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h) uint32_t src_w, uint32_t src_h)
{ {
struct nvif_device *dev = &nouveau_drm(plane->dev)->device; struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object;
struct nouveau_plane *nv_plane = struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base); container_of(plane, struct nouveau_plane, base);
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
@@ -426,7 +427,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
static int static int
nv04_disable_plane(struct drm_plane *plane) nv04_disable_plane(struct drm_plane *plane)
{ {
struct nvif_device *dev = &nouveau_drm(plane->dev)->device; struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object;
struct nouveau_plane *nv_plane = struct nouveau_plane *nv_plane =
container_of(plane, struct nouveau_plane, base); container_of(plane, struct nouveau_plane, base);
drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
+10 -6
View File
@@ -35,7 +35,7 @@
#include <drm/i2c/ch7006.h> #include <drm/i2c/ch7006.h>
static struct nvkm_i2c_board_info nv04_tv_encoder_info[] = { static struct nvkm_i2c_bus_probe nv04_tv_encoder_info[] = {
{ {
{ {
I2C_BOARD_INFO("ch7006", 0x75), I2C_BOARD_INFO("ch7006", 0x75),
@@ -55,9 +55,13 @@ int nv04_tv_identify(struct drm_device *dev, int i2c_index)
{ {
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, i2c_index);
return i2c->identify(i2c, i2c_index, "TV encoder", if (bus) {
nv04_tv_encoder_info, NULL, NULL); return nvkm_i2c_bus_probe(bus, "TV encoder",
nv04_tv_encoder_info,
NULL, NULL);
}
return -ENODEV;
} }
@@ -205,7 +209,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
struct drm_device *dev = connector->dev; struct drm_device *dev = connector->dev;
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
struct nvkm_i2c_port *port = i2c->find(i2c, entry->i2c_index); struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, entry->i2c_index);
int type, ret; int type, ret;
/* Ensure that we can talk to this encoder */ /* Ensure that we can talk to this encoder */
@@ -231,7 +235,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
/* Run the slave-specific initialization */ /* Run the slave-specific initialization */
ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder), ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
&port->adapter, &bus->i2c,
&nv04_tv_encoder_info[type].dev); &nv04_tv_encoder_info[type].dev);
if (ret < 0) if (ret < 0)
goto fail_cleanup; goto fail_cleanup;
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
+11 -19
View File
@@ -62,8 +62,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
head = (dacclk & 0x100) >> 8; head = (dacclk & 0x100) >> 8;
/* Save the previous state. */ /* Save the previous state. */
gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff); gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff); gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
@@ -74,8 +74,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
/* Prepare the DAC for load detection. */ /* Prepare the DAC for load detection. */
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
@@ -120,8 +120,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
return sample; return sample;
} }
@@ -130,18 +130,10 @@ static bool
get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
{ {
struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device; struct nvkm_device *device = nvxx_device(&drm->device);
/* Zotac FX5200 */ if (device->quirk && device->quirk->tv_pin_mask) {
if (nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x1035) || *pin_mask = device->quirk->tv_pin_mask;
nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x2035)) {
*pin_mask = 0xc;
return false;
}
/* MSI nForce2 IGP */
if (nv_device_match(nvxx_object(device), 0x01f0, 0x1462, 0x5710)) {
*pin_mask = 0xc;
return false; return false;
} }
@@ -395,8 +387,8 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
nv_load_ptv(dev, regs, 200); nv_load_ptv(dev, regs, 200);
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON); nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
} }
drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
+2 -2
View File
@@ -131,13 +131,13 @@ static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
uint32_t val) uint32_t val)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_device *device = &nouveau_drm(dev)->device;
nvif_wr32(device, reg, val); nvif_wr32(&device->object, reg, val);
} }
static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
{ {
struct nvif_device *device = &nouveau_drm(dev)->device; struct nvif_device *device = &nouveau_drm(dev)->device;
return nvif_rd32(device, reg); return nvif_rd32(&device->object, reg);
} }
static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg, static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
drivers/gpu/drm/nouveau/include/nvif/class.h
+147 -58
View File
@@ -45,6 +45,11 @@
#define GM107_DISP 0x00009470 #define GM107_DISP 0x00009470
#define GM204_DISP 0x00009570 #define GM204_DISP 0x00009570
#define NV31_MPEG 0x00003174
#define G82_MPEG 0x00008274
#define NV74_VP2 0x00007476
#define NV50_DISP_CURSOR 0x0000507a #define NV50_DISP_CURSOR 0x0000507a
#define G82_DISP_CURSOR 0x0000827a #define G82_DISP_CURSOR 0x0000827a
#define GT214_DISP_CURSOR 0x0000857a #define GT214_DISP_CURSOR 0x0000857a
@@ -94,15 +99,40 @@
#define MAXWELL_A 0x0000b097 #define MAXWELL_A 0x0000b097
#define MAXWELL_B 0x0000b197 #define MAXWELL_B 0x0000b197
#define NV74_BSP 0x000074b0
#define GT212_MSVLD 0x000085b1
#define IGT21A_MSVLD 0x000086b1
#define G98_MSVLD 0x000088b1
#define GF100_MSVLD 0x000090b1
#define GK104_MSVLD 0x000095b1
#define GT212_MSPDEC 0x000085b2
#define G98_MSPDEC 0x000088b2
#define GF100_MSPDEC 0x000090b2
#define GK104_MSPDEC 0x000095b2
#define GT212_MSPPP 0x000085b3
#define G98_MSPPP 0x000088b3
#define GF100_MSPPP 0x000090b3
#define G98_SEC 0x000088b4
#define GT212_DMA 0x000085b5
#define FERMI_DMA 0x000090b5
#define KEPLER_DMA_COPY_A 0x0000a0b5
#define MAXWELL_DMA_COPY_A 0x0000b0b5
#define FERMI_DECOMPRESS 0x000090b8
#define FERMI_COMPUTE_A 0x000090c0 #define FERMI_COMPUTE_A 0x000090c0
#define FERMI_COMPUTE_B 0x000091c0 #define FERMI_COMPUTE_B 0x000091c0
#define KEPLER_COMPUTE_A 0x0000a0c0 #define KEPLER_COMPUTE_A 0x0000a0c0
#define KEPLER_COMPUTE_B 0x0000a1c0 #define KEPLER_COMPUTE_B 0x0000a1c0
#define MAXWELL_COMPUTE_A 0x0000b0c0 #define MAXWELL_COMPUTE_A 0x0000b0c0
#define MAXWELL_COMPUTE_B 0x0000b1c0 #define MAXWELL_COMPUTE_B 0x0000b1c0
#define NV74_CIPHER 0x000074c1
/******************************************************************************* /*******************************************************************************
* client * client
@@ -126,32 +156,10 @@ struct nv_device_v0 {
__u8 version; __u8 version;
__u8 pad01[7]; __u8 pad01[7];
__u64 device; /* device identifier, ~0 for client default */ __u64 device; /* device identifier, ~0 for client default */
#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL
#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL
#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL
__u64 disable; /* disable particular subsystems */
__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
}; };
#define NV_DEVICE_V0_INFO 0x00 #define NV_DEVICE_V0_INFO 0x00
#define NV_DEVICE_V0_TIME 0x01
struct nv_device_info_v0 { struct nv_device_info_v0 {
__u8 version; __u8 version;
@@ -176,6 +184,14 @@ struct nv_device_info_v0 {
__u8 pad06[2]; __u8 pad06[2];
__u64 ram_size; __u64 ram_size;
__u64 ram_user; __u64 ram_user;
char chip[16];
char name[64];
};
struct nv_device_time_v0 {
__u8 version;
__u8 pad01[7];
__u64 time;
}; };
@@ -235,13 +251,13 @@ struct gf100_dma_v0 {
__u8 pad03[5]; __u8 pad03[5];
}; };
struct gf110_dma_v0 { struct gf119_dma_v0 {
__u8 version; __u8 version;
#define GF110_DMA_V0_PAGE_LP 0x00 #define GF119_DMA_V0_PAGE_LP 0x00
#define GF110_DMA_V0_PAGE_SP 0x01 #define GF119_DMA_V0_PAGE_SP 0x01
__u8 page; __u8 page;
#define GF110_DMA_V0_KIND_PITCH 0x00 #define GF119_DMA_V0_KIND_PITCH 0x00
#define GF110_DMA_V0_KIND_VM 0xff #define GF119_DMA_V0_KIND_VM 0xff
__u8 kind; __u8 kind;
__u8 pad03[5]; __u8 pad03[5];
}; };
@@ -251,33 +267,74 @@ struct gf110_dma_v0 {
* perfmon * perfmon
******************************************************************************/ ******************************************************************************/
struct nvif_perfctr_v0 { #define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00
__u8 version; #define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01
__u8 pad01[1]; #define NVIF_PERFMON_V0_QUERY_SOURCE 0x02
__u16 logic_op;
__u8 pad04[4];
char name[4][64];
};
#define NVIF_PERFCTR_V0_QUERY 0x00 struct nvif_perfmon_query_domain_v0 {
#define NVIF_PERFCTR_V0_SAMPLE 0x01
#define NVIF_PERFCTR_V0_READ 0x02
struct nvif_perfctr_query_v0 {
__u8 version; __u8 version;
__u8 pad01[3]; __u8 id;
__u32 iter; __u8 counter_nr;
__u8 iter;
__u16 signal_nr;
__u8 pad05[2];
char name[64]; char name[64];
}; };
struct nvif_perfctr_sample { struct nvif_perfmon_query_signal_v0 {
__u8 version;
__u8 domain;
__u16 iter;
__u8 signal;
__u8 source_nr;
__u8 pad05[2];
char name[64];
}; };
struct nvif_perfctr_read_v0 { struct nvif_perfmon_query_source_v0 {
__u8 version;
__u8 domain;
__u8 signal;
__u8 iter;
__u8 pad04[4];
__u32 source;
__u32 mask;
char name[64];
};
/*******************************************************************************
* perfdom
******************************************************************************/
struct nvif_perfdom_v0 {
__u8 version;
__u8 domain;
__u8 mode;
__u8 pad03[1];
struct {
__u8 signal[4];
__u64 source[4][8];
__u16 logic_op;
} ctr[4];
};
#define NVIF_PERFDOM_V0_INIT 0x00
#define NVIF_PERFDOM_V0_SAMPLE 0x01
#define NVIF_PERFDOM_V0_READ 0x02
struct nvif_perfdom_init {
};
struct nvif_perfdom_sample {
};
struct nvif_perfdom_read_v0 {
__u8 version; __u8 version;
__u8 pad01[7]; __u8 pad01[7];
__u32 ctr; __u32 ctr[4];
__u32 clk; __u32 clk;
__u8 pad04[4];
}; };
@@ -337,7 +394,16 @@ struct nv03_channel_dma_v0 {
__u8 version; __u8 version;
__u8 chid; __u8 chid;
__u8 pad02[2]; __u8 pad02[2];
__u32 pushbuf; __u32 offset;
__u64 pushbuf;
};
struct nv50_channel_dma_v0 {
__u8 version;
__u8 chid;
__u8 pad02[6];
__u64 vm;
__u64 pushbuf;
__u64 offset; __u64 offset;
}; };
@@ -350,10 +416,20 @@ struct nv03_channel_dma_v0 {
struct nv50_channel_gpfifo_v0 { struct nv50_channel_gpfifo_v0 {
__u8 version; __u8 version;
__u8 chid; __u8 chid;
__u8 pad01[6]; __u8 pad02[2];
__u32 pushbuf;
__u32 ilength; __u32 ilength;
__u64 ioffset; __u64 ioffset;
__u64 pushbuf;
__u64 vm;
};
struct fermi_channel_gpfifo_v0 {
__u8 version;
__u8 chid;
__u8 pad02[2];
__u32 ilength;
__u64 ioffset;
__u64 vm;
}; };
struct kepler_channel_gpfifo_a_v0 { struct kepler_channel_gpfifo_a_v0 {
@@ -367,10 +443,9 @@ struct kepler_channel_gpfifo_a_v0 {
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
__u8 engine; __u8 engine;
__u16 chid; __u16 chid;
__u8 pad04[4];
__u32 pushbuf;
__u32 ilength; __u32 ilength;
__u64 ioffset; __u64 ioffset;
__u64 vm;
}; };
/******************************************************************************* /*******************************************************************************
@@ -491,8 +566,8 @@ struct nv50_disp_pior_pwr_v0 {
/* core */ /* core */
struct nv50_disp_core_channel_dma_v0 { struct nv50_disp_core_channel_dma_v0 {
__u8 version; __u8 version;
__u8 pad01[3]; __u8 pad01[7];
__u32 pushbuf; __u64 pushbuf;
}; };
#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
@@ -509,9 +584,9 @@ struct nv50_disp_cursor_v0 {
/* base */ /* base */
struct nv50_disp_base_channel_dma_v0 { struct nv50_disp_base_channel_dma_v0 {
__u8 version; __u8 version;
__u8 pad01[2];
__u8 head; __u8 head;
__u32 pushbuf; __u8 pad02[6];
__u64 pushbuf;
}; };
#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
@@ -519,9 +594,9 @@ struct nv50_disp_base_channel_dma_v0 {
/* overlay */ /* overlay */
struct nv50_disp_overlay_channel_dma_v0 { struct nv50_disp_overlay_channel_dma_v0 {
__u8 version; __u8 version;
__u8 pad01[2];
__u8 head; __u8 head;
__u32 pushbuf; __u8 pad02[6];
__u64 pushbuf;
}; };
#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
@@ -535,6 +610,20 @@ struct nv50_disp_overlay_v0 {
#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
/*******************************************************************************
* software
******************************************************************************/
#define NVSW_NTFY_UEVENT 0x00
#define NV04_NVSW_GET_REF 0x00
struct nv04_nvsw_get_ref_v0 {
__u8 version;
__u8 pad01[3];
__u32 ref;
};
/******************************************************************************* /*******************************************************************************
* fermi * fermi
******************************************************************************/ ******************************************************************************/
drivers/gpu/drm/nouveau/include/nvif/client.h
+8 -19
View File
@@ -4,36 +4,25 @@
#include <nvif/object.h> #include <nvif/object.h>
struct nvif_client { struct nvif_client {
struct nvif_object base; struct nvif_object object;
struct nvif_object *object; /*XXX: hack for nvif_object() */
const struct nvif_driver *driver; const struct nvif_driver *driver;
u64 version;
u8 route;
bool super; bool super;
}; };
static inline struct nvif_client * int nvif_client_init(const char *drv, const char *name, u64 device,
nvif_client(struct nvif_object *object) const char *cfg, const char *dbg,
{
while (object && object->parent != object)
object = object->parent;
return (void *)object;
}
int nvif_client_init(void (*dtor)(struct nvif_client *), const char *,
const char *, u64, const char *, const char *,
struct nvif_client *); struct nvif_client *);
void nvif_client_fini(struct nvif_client *); void nvif_client_fini(struct nvif_client *);
int nvif_client_new(const char *, const char *, u64, const char *,
const char *, struct nvif_client **);
void nvif_client_ref(struct nvif_client *, struct nvif_client **);
int nvif_client_ioctl(struct nvif_client *, void *, u32); int nvif_client_ioctl(struct nvif_client *, void *, u32);
int nvif_client_suspend(struct nvif_client *); int nvif_client_suspend(struct nvif_client *);
int nvif_client_resume(struct nvif_client *); int nvif_client_resume(struct nvif_client *);
/*XXX*/ /*XXX*/
#include <core/client.h> #include <core/client.h>
#define nvxx_client(a) ({ \ #define nvxx_client(a) ({ \
struct nvif_client *_client = nvif_client(nvif_object(a)); \ struct nvif_client *_client = (a); \
nvkm_client(_client->base.priv); \ (struct nvkm_client *)_client->object.priv; \
}) })
#endif #endif
drivers/gpu/drm/nouveau/include/nvif/device.h
+43 -30
View File
@@ -5,26 +5,35 @@
#include <nvif/class.h> #include <nvif/class.h>
struct nvif_device { struct nvif_device {
struct nvif_object base; struct nvif_object object;
struct nvif_object *object; /*XXX: hack for nvif_object() */
struct nv_device_info_v0 info; struct nv_device_info_v0 info;
}; };
static inline struct nvif_device * int nvif_device_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32,
nvif_device(struct nvif_object *object)
{
while (object && object->oclass != 0x0080 /*XXX: NV_DEVICE_CLASS*/ )
object = object->parent;
return (void *)object;
}
int nvif_device_init(struct nvif_object *, void (*dtor)(struct nvif_device *),
u32 handle, u32 oclass, void *, u32,
struct nvif_device *); struct nvif_device *);
void nvif_device_fini(struct nvif_device *); void nvif_device_fini(struct nvif_device *);
int nvif_device_new(struct nvif_object *, u32 handle, u32 oclass, u64 nvif_device_time(struct nvif_device *);
void *, u32, struct nvif_device **);
void nvif_device_ref(struct nvif_device *, struct nvif_device **); /* Delay based on GPU time (ie. PTIMER).
*
* Will return -ETIMEDOUT unless the loop was terminated with 'break',
* where it will return the number of nanoseconds taken instead.
*/
#define nvif_nsec(d,n,cond...) ({ \
struct nvif_device *_device = (d); \
u64 _nsecs = (n), _time0 = nvif_device_time(_device); \
s64 _taken = 0; \
\
do { \
cond \
} while (_taken = nvif_device_time(_device) - _time0, _taken < _nsecs);\
\
if (_taken >= _nsecs) \
_taken = -ETIMEDOUT; \
_taken; \
})
#define nvif_usec(d,u,cond...) nvif_nsec((d), (u) * 1000, ##cond)
#define nvif_msec(d,m,cond...) nvif_usec((d), (m) * 1000, ##cond)
/*XXX*/ /*XXX*/
#include <subdev/bios.h> #include <subdev/bios.h>
@@ -36,26 +45,30 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
#include <subdev/i2c.h> #include <subdev/i2c.h>
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/therm.h> #include <subdev/therm.h>
#include <subdev/pci.h>
#define nvxx_device(a) nv_device(nvxx_object((a))) #define nvxx_device(a) ({ \
#define nvxx_bios(a) nvkm_bios(nvxx_device(a)) struct nvif_device *_device = (a); \
#define nvxx_fb(a) nvkm_fb(nvxx_device(a)) struct { \
#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a)) struct nvkm_object object; \
#define nvxx_bar(a) nvkm_bar(nvxx_device(a)) struct nvkm_device *device; \
#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a)) } *_udevice = _device->object.priv; \
#define nvxx_clk(a) nvkm_clk(nvxx_device(a)) _udevice->device; \
#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a)) })
#define nvxx_timer(a) nvkm_timer(nvxx_device(a)) #define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_wait(a,b,c,d) nv_wait(nvxx_timer(a), (b), (c), (d)) #define nvxx_fb(a) nvxx_device(a)->fb
#define nvxx_wait_cb(a,b,c) nv_wait_cb(nvxx_timer(a), (b), (c)) #define nvxx_mmu(a) nvxx_device(a)->mmu
#define nvxx_therm(a) nvkm_therm(nvxx_device(a)) #define nvxx_bar(a) nvxx_device(a)->bar
#define nvxx_gpio(a) nvxx_device(a)->gpio
#define nvxx_clk(a) nvxx_device(a)->clk
#define nvxx_i2c(a) nvxx_device(a)->i2c
#define nvxx_therm(a) nvxx_device(a)->therm
#include <core/device.h> #include <core/device.h>
#include <engine/fifo.h> #include <engine/fifo.h>
#include <engine/gr.h> #include <engine/gr.h>
#include <engine/sw.h> #include <engine/sw.h>
#define nvxx_fifo(a) nvkm_fifo(nvxx_device(a)) #define nvxx_fifo(a) nvxx_device(a)->fifo
#define nvxx_fifo_chan(a) ((struct nvkm_fifo_chan *)nvxx_object(a)) #define nvxx_gr(a) nvxx_device(a)->gr
#define nvxx_gr(a) ((struct nvkm_gr *)nvkm_engine(nvxx_object(a), NVDEV_ENGINE_GR))
#endif #endif
drivers/gpu/drm/nouveau/include/nvif/ioctl.h
+23 -11
View File
@@ -1,11 +1,10 @@
#ifndef __NVIF_IOCTL_H__ #ifndef __NVIF_IOCTL_H__
#define __NVIF_IOCTL_H__ #define __NVIF_IOCTL_H__
#define NVIF_VERSION_LATEST 0x0000000000000000ULL
struct nvif_ioctl_v0 { struct nvif_ioctl_v0 {
__u8 version; __u8 version;
#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
#define NVIF_IOCTL_V0_OWNER_ANY 0xff
__u8 owner;
#define NVIF_IOCTL_V0_NOP 0x00 #define NVIF_IOCTL_V0_NOP 0x00
#define NVIF_IOCTL_V0_SCLASS 0x01 #define NVIF_IOCTL_V0_SCLASS 0x01
#define NVIF_IOCTL_V0_NEW 0x02 #define NVIF_IOCTL_V0_NEW 0x02
@@ -20,17 +19,20 @@ struct nvif_ioctl_v0 {
#define NVIF_IOCTL_V0_NTFY_GET 0x0b #define NVIF_IOCTL_V0_NTFY_GET 0x0b
#define NVIF_IOCTL_V0_NTFY_PUT 0x0c #define NVIF_IOCTL_V0_NTFY_PUT 0x0c
__u8 type; __u8 type;
__u8 path_nr; __u8 pad02[4];
#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
#define NVIF_IOCTL_V0_OWNER_ANY 0xff
__u8 owner;
#define NVIF_IOCTL_V0_ROUTE_NVIF 0x00 #define NVIF_IOCTL_V0_ROUTE_NVIF 0x00
#define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff #define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff
__u8 pad04[3];
__u8 route; __u8 route;
__u64 token; __u64 token;
__u32 path[8]; /* in reverse */ __u64 object;
__u8 data[]; /* ioctl data (below) */ __u8 data[]; /* ioctl data (below) */
}; };
struct nvif_ioctl_nop { struct nvif_ioctl_nop_v0 {
__u64 version;
}; };
struct nvif_ioctl_sclass_v0 { struct nvif_ioctl_sclass_v0 {
@@ -38,7 +40,11 @@ struct nvif_ioctl_sclass_v0 {
__u8 version; __u8 version;
__u8 count; __u8 count;
__u8 pad02[6]; __u8 pad02[6];
__u32 oclass[]; struct nvif_ioctl_sclass_oclass_v0 {
__s32 oclass;
__s16 minver;
__s16 maxver;
} oclass[];
}; };
struct nvif_ioctl_new_v0 { struct nvif_ioctl_new_v0 {
@@ -47,11 +53,17 @@ struct nvif_ioctl_new_v0 {
__u8 pad01[6]; __u8 pad01[6];
__u8 route; __u8 route;
__u64 token; __u64 token;
__u64 object;
__u32 handle; __u32 handle;
/* these class numbers are made up by us, and not nvidia-assigned */ /* these class numbers are made up by us, and not nvidia-assigned */
#define NVIF_IOCTL_NEW_V0_PERFCTR 0x0000ffff #define NVIF_IOCTL_NEW_V0_CONTROL -1
#define NVIF_IOCTL_NEW_V0_CONTROL 0x0000fffe #define NVIF_IOCTL_NEW_V0_PERFMON -2
__u32 oclass; #define NVIF_IOCTL_NEW_V0_PERFDOM -3
#define NVIF_IOCTL_NEW_V0_SW_NV04 -4
#define NVIF_IOCTL_NEW_V0_SW_NV10 -5
#define NVIF_IOCTL_NEW_V0_SW_NV50 -6
#define NVIF_IOCTL_NEW_V0_SW_GF100 -7
__s32 oclass;
__u8 data[]; /* class data (class.h) */ __u8 data[]; /* class data (class.h) */
}; };
drivers/gpu/drm/nouveau/include/nvif/notify.h
+3 -9
View File
@@ -23,17 +23,11 @@ struct nvif_notify {
struct work_struct work; struct work_struct work;
}; };
int nvif_notify_init(struct nvif_object *, void (*dtor)(struct nvif_notify *), int nvif_notify_init(struct nvif_object *, int (*func)(struct nvif_notify *),
int (*func)(struct nvif_notify *), bool work, u8 type, bool work, u8 type, void *data, u32 size, u32 reply,
void *data, u32 size, u32 reply, struct nvif_notify *); struct nvif_notify *);
int nvif_notify_fini(struct nvif_notify *); int nvif_notify_fini(struct nvif_notify *);
int nvif_notify_get(struct nvif_notify *); int nvif_notify_get(struct nvif_notify *);
int nvif_notify_put(struct nvif_notify *); int nvif_notify_put(struct nvif_notify *);
int nvif_notify(const void *, u32, const void *, u32); int nvif_notify(const void *, u32, const void *, u32);
int nvif_notify_new(struct nvif_object *, int (*func)(struct nvif_notify *),
bool work, u8 type, void *data, u32 size, u32 reply,
struct nvif_notify **);
void nvif_notify_ref(struct nvif_notify *, struct nvif_notify **);
#endif #endif
drivers/gpu/drm/nouveau/include/nvif/object.h
+35 -35
View File
@@ -3,73 +3,73 @@
#include <nvif/os.h> #include <nvif/os.h>
struct nvif_sclass {
s32 oclass;
int minver;
int maxver;
};
struct nvif_object { struct nvif_object {
struct nvif_object *parent; struct nvif_client *client;
struct nvif_object *object; /*XXX: hack for nvif_object() */
struct kref refcount;
u32 handle; u32 handle;
u32 oclass; s32 oclass;
void *data;
u32 size;
void *priv; /*XXX: hack */ void *priv; /*XXX: hack */
void (*dtor)(struct nvif_object *);
struct { struct {
void __iomem *ptr; void __iomem *ptr;
u32 size; u32 size;
} map; } map;
}; };
int nvif_object_init(struct nvif_object *, void (*dtor)(struct nvif_object *), int nvif_object_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32,
u32 handle, u32 oclass, void *, u32,
struct nvif_object *); struct nvif_object *);
void nvif_object_fini(struct nvif_object *); void nvif_object_fini(struct nvif_object *);
int nvif_object_new(struct nvif_object *, u32 handle, u32 oclass,
void *, u32, struct nvif_object **);
void nvif_object_ref(struct nvif_object *, struct nvif_object **);
int nvif_object_ioctl(struct nvif_object *, void *, u32, void **); int nvif_object_ioctl(struct nvif_object *, void *, u32, void **);
int nvif_object_sclass(struct nvif_object *, u32 *, int); int nvif_object_sclass_get(struct nvif_object *, struct nvif_sclass **);
void nvif_object_sclass_put(struct nvif_sclass **);
u32 nvif_object_rd(struct nvif_object *, int, u64); u32 nvif_object_rd(struct nvif_object *, int, u64);
void nvif_object_wr(struct nvif_object *, int, u64, u32); void nvif_object_wr(struct nvif_object *, int, u64, u32);
int nvif_object_mthd(struct nvif_object *, u32, void *, u32); int nvif_object_mthd(struct nvif_object *, u32, void *, u32);
int nvif_object_map(struct nvif_object *); int nvif_object_map(struct nvif_object *);
void nvif_object_unmap(struct nvif_object *); void nvif_object_unmap(struct nvif_object *);
#define nvif_handle(a) (unsigned long)(void *)(a)
#define nvif_object(a) (a)->object #define nvif_object(a) (a)->object
#define ioread8_native ioread8 #define nvif_rd(a,f,b,c) ({ \
#define iowrite8_native iowrite8 struct nvif_object *_object = (a); \
#define nvif_rd(a,b,c) ({ \
struct nvif_object *_object = nvif_object(a); \
u32 _data; \ u32 _data; \
if (likely(_object->map.ptr)) \ if (likely(_object->map.ptr)) \
_data = ioread##b##_native((u8 __iomem *)_object->map.ptr + (c)); \ _data = f((u8 __iomem *)_object->map.ptr + (c)); \
else \ else \
_data = nvif_object_rd(_object, (b) / 8, (c)); \ _data = nvif_object_rd(_object, (b), (c)); \
_data; \ _data; \
}) })
#define nvif_wr(a,b,c,d) ({ \ #define nvif_wr(a,f,b,c,d) ({ \
struct nvif_object *_object = nvif_object(a); \ struct nvif_object *_object = (a); \
if (likely(_object->map.ptr)) \ if (likely(_object->map.ptr)) \
iowrite##b##_native((d), (u8 __iomem *)_object->map.ptr + (c)); \ f((d), (u8 __iomem *)_object->map.ptr + (c)); \
else \ else \
nvif_object_wr(_object, (b) / 8, (c), (d)); \ nvif_object_wr(_object, (b), (c), (d)); \
}) })
#define nvif_rd08(a,b) ({ u8 _v = nvif_rd((a), 8, (b)); _v; }) #define nvif_rd08(a,b) ({ ((u8)nvif_rd((a), ioread8, 1, (b))); })
#define nvif_rd16(a,b) ({ u16 _v = nvif_rd((a), 16, (b)); _v; }) #define nvif_rd16(a,b) ({ ((u16)nvif_rd((a), ioread16_native, 2, (b))); })
#define nvif_rd32(a,b) ({ u32 _v = nvif_rd((a), 32, (b)); _v; }) #define nvif_rd32(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); })
#define nvif_wr08(a,b,c) nvif_wr((a), 8, (b), (u8)(c)) #define nvif_wr08(a,b,c) nvif_wr((a), iowrite8, 1, (b), (u8)(c))
#define nvif_wr16(a,b,c) nvif_wr((a), 16, (b), (u16)(c)) #define nvif_wr16(a,b,c) nvif_wr((a), iowrite16_native, 2, (b), (u16)(c))
#define nvif_wr32(a,b,c) nvif_wr((a), 32, (b), (u32)(c)) #define nvif_wr32(a,b,c) nvif_wr((a), iowrite32_native, 4, (b), (u32)(c))
#define nvif_mask(a,b,c,d) ({ \ #define nvif_mask(a,b,c,d) ({ \
u32 _v = nvif_rd32(nvif_object(a), (b)); \ struct nvif_object *__object = (a); \
nvif_wr32(nvif_object(a), (b), (_v & ~(c)) | (d)); \ u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
_v; \ nvif_wr32(__object, _addr, (_data & ~(c)) | (d)); \
_data; \
}) })
#define nvif_mthd(a,b,c,d) nvif_object_mthd(nvif_object(a), (b), (c), (d)) #define nvif_mthd(a,b,c,d) nvif_object_mthd((a), (b), (c), (d))
/*XXX*/ /*XXX*/
#include <core/object.h> #include <core/object.h>
#define nvxx_object(a) ((struct nvkm_object *)nvif_object(a)->priv) #define nvxx_object(a) ({ \
struct nvif_object *_object = (a); \
(struct nvkm_object *)_object->priv; \
})
#endif #endif
drivers/gpu/drm/nouveau/include/nvif/os.h
+6 -1
View File
@@ -24,9 +24,15 @@
#include <linux/power_supply.h> #include <linux/power_supply.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
#include <linux/agp_backend.h>
#include <linux/reset.h>
#include <linux/iommu.h>
#include <asm/unaligned.h> #include <asm/unaligned.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pmc.h>
#ifndef ioread32_native #ifndef ioread32_native
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
#define ioread16_native ioread16be #define ioread16_native ioread16be
@@ -40,5 +46,4 @@
#define iowrite32_native iowrite32 #define iowrite32_native iowrite32
#endif /* def __BIG_ENDIAN else */ #endif /* def __BIG_ENDIAN else */
#endif /* !ioread32_native */ #endif /* !ioread32_native */
#endif #endif
drivers/gpu/drm/nouveau/include/nvkm/core/client.h
+31 -34
View File
@@ -1,55 +1,52 @@
#ifndef __NVKM_CLIENT_H__ #ifndef __NVKM_CLIENT_H__
#define __NVKM_CLIENT_H__ #define __NVKM_CLIENT_H__
#include <core/namedb.h> #include <core/object.h>
struct nvkm_client { struct nvkm_client {
struct nvkm_namedb namedb; struct nvkm_object object;
struct nvkm_handle *root;
struct nvkm_object *device;
char name[32]; char name[32];
u64 device;
u32 debug; u32 debug;
struct nvkm_vm *vm;
struct nvkm_client_notify *notify[16];
struct rb_root objroot;
struct rb_root dmaroot;
bool super; bool super;
void *data; void *data;
int (*ntfy)(const void *, u32, const void *, u32); int (*ntfy)(const void *, u32, const void *, u32);
struct nvkm_client_notify *notify[16];
struct nvkm_vm *vm;
}; };
static inline struct nvkm_client * bool nvkm_client_insert(struct nvkm_client *, struct nvkm_object *);
nv_client(void *obj) void nvkm_client_remove(struct nvkm_client *, struct nvkm_object *);
{ struct nvkm_object *nvkm_client_search(struct nvkm_client *, u64 object);
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if (unlikely(!nv_iclass(obj, NV_CLIENT_CLASS)))
nv_assert("BAD CAST -> NvClient, %08x", nv_hclass(obj));
#endif
return obj;
}
static inline struct nvkm_client *
nvkm_client(void *obj)
{
struct nvkm_object *client = nv_object(obj);
while (client && !(nv_iclass(client, NV_CLIENT_CLASS)))
client = client->parent;
return (void *)client;
}
#define nvkm_client_create(n,c,oc,od,d) \
nvkm_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d)
int nvkm_client_create_(const char *name, u64 device, const char *cfg,
const char *dbg, int, void **);
#define nvkm_client_destroy(p) \
nvkm_namedb_destroy(&(p)->base)
int nvkm_client_new(const char *name, u64 device, const char *cfg,
const char *dbg, struct nvkm_client **);
void nvkm_client_del(struct nvkm_client **);
int nvkm_client_init(struct nvkm_client *); int nvkm_client_init(struct nvkm_client *);
int nvkm_client_fini(struct nvkm_client *, bool suspend); int nvkm_client_fini(struct nvkm_client *, bool suspend);
const char *nvkm_client_name(void *obj);
int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *, int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *,
void *data, u32 size); void *data, u32 size);
int nvkm_client_notify_del(struct nvkm_client *, int index); int nvkm_client_notify_del(struct nvkm_client *, int index);
int nvkm_client_notify_get(struct nvkm_client *, int index); int nvkm_client_notify_get(struct nvkm_client *, int index);
int nvkm_client_notify_put(struct nvkm_client *, int index); int nvkm_client_notify_put(struct nvkm_client *, int index);
/* logging for client-facing objects */
#define nvif_printk(o,l,p,f,a...) do { \
struct nvkm_object *_object = (o); \
struct nvkm_client *_client = _object->client; \
if (_client->debug >= NV_DBG_##l) \
printk(KERN_##p "nouveau: %s:%08x:%08x: "f, _client->name, \
_object->handle, _object->oclass, ##a); \
} while(0)
#define nvif_fatal(o,f,a...) nvif_printk((o), FATAL, CRIT, f, ##a)
#define nvif_error(o,f,a...) nvif_printk((o), ERROR, ERR, f, ##a)
#define nvif_debug(o,f,a...) nvif_printk((o), DEBUG, INFO, f, ##a)
#define nvif_trace(o,f,a...) nvif_printk((o), TRACE, INFO, f, ##a)
#define nvif_info(o,f,a...) nvif_printk((o), INFO, INFO, f, ##a)
#define nvif_ioctl(o,f,a...) nvif_trace((o), "ioctl: "f, ##a)
#endif #endif

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