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Fix common misspellings

Browse Source 
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
This commit is contained in:
Lucas De Marchi
2011-03-30 22:57:33 -03:00
parent 6aba74f279
commit 25985edced
2463 changed files with 4252 additions and 4252 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/scsi/3w-9xxx.h
+1 -1
View File
@@ -61,7 +61,7 @@ static twa_message_type twa_aen_table[] = {
{0x0000, "AEN queue empty"},
{0x0001, "Controller reset occurred"},
{0x0002, "Degraded unit detected"},
{0x0003, "Controller error occured"},
{0x0003, "Controller error occurred"},
{0x0004, "Background rebuild failed"},
{0x0005, "Background rebuild done"},
{0x0006, "Incomplete unit detected"},
drivers/scsi/3w-xxxx.h
+1 -1
View File
@@ -8,7 +8,7 @@
Copyright (C) 1999-2010 3ware Inc.
Kernel compatiblity By: Andre Hedrick <andre@suse.com>
Kernel compatibility By: Andre Hedrick <andre@suse.com>
Non-Copyright (C) 2000 Andre Hedrick <andre@suse.com>
This program is free software; you can redistribute it and/or modify
drivers/scsi/53c700.scr
+1 -1
View File
@@ -31,7 +31,7 @@ ABSOLUTE StatusAddress = 0 ; Addr to receive status return
ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
;
; This is the magic component for handling scatter-gather. Each of the
; SG components is preceeded by a script fragment which moves the
; SG components is preceded by a script fragment which moves the
; necessary amount of data and jumps to the next SG segment. The final
; SG segment jumps back to . However, this address is the first SG script
; segment.
drivers/scsi/53c700_d.h_shipped
+1 -1
View File
@@ -34,7 +34,7 @@ ABSOLUTE StatusAddress = 0 ; Addr to receive status return
ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
;
; This is the magic component for handling scatter-gather. Each of the
; SG components is preceeded by a script fragment which moves the
; SG components is preceded by a script fragment which moves the
; necessary amount of data and jumps to the next SG segment. The final
; SG segment jumps back to . However, this address is the first SG script
; segment.
drivers/scsi/FlashPoint.c
+2 -2
View File
@@ -2509,7 +2509,7 @@ static void FPT_ssel(unsigned long port, unsigned char p_card)
WR_HARPOON(port + hp_autostart_3,
(SELECT + SELCHK_STRT));
/* Setup our STATE so we know what happend when
/* Setup our STATE so we know what happened when
the wheels fall off. */
currSCCB->Sccb_scsistat = SELECT_ST;
@@ -2900,7 +2900,7 @@ static void FPT_SendMsg(unsigned long port, unsigned char message)
*
* Function: FPT_sdecm
*
* Description: Determine the proper responce to the message from the
* Description: Determine the proper response to the message from the
* target device.
*
*---------------------------------------------------------------------*/
drivers/scsi/NCR5380.c
+4 -4
View File
@@ -1198,12 +1198,12 @@ static irqreturn_t NCR5380_intr(int dummy, void *dev_id)
*/
if ((NCR5380_read(MODE_REG) & MR_DMA) && ((basr & BASR_END_DMA_TRANSFER) || !(basr & BASR_PHASE_MATCH))) {
int transfered;
int transferred;
if (!hostdata->connected)
panic("scsi%d : received end of DMA interrupt with no connected cmd\n", instance->hostno);
transfered = (hostdata->dmalen - NCR5380_dma_residual(instance));
transferred = (hostdata->dmalen - NCR5380_dma_residual(instance));
hostdata->connected->SCp.this_residual -= transferred;
hostdata->connected->SCp.ptr += transferred;
hostdata->dmalen = 0;
@@ -1563,7 +1563,7 @@ failed:
* bytes to transfer, **data - pointer to data pointer.
*
* Returns : -1 when different phase is entered without transferring
* maximum number of bytes, 0 if all bytes or transfered or exit
* maximum number of bytes, 0 if all bytes or transferred or exit
* is in same phase.
*
* Also, *phase, *count, *data are modified in place.
@@ -1800,7 +1800,7 @@ static int do_abort(struct Scsi_Host *host) {
* bytes to transfer, **data - pointer to data pointer.
*
* Returns : -1 when different phase is entered without transferring
* maximum number of bytes, 0 if all bytes or transfered or exit
* maximum number of bytes, 0 if all bytes or transferred or exit
* is in same phase.
*
* Also, *phase, *count, *data are modified in place.
drivers/scsi/aacraid/aachba.c
+2 -2
View File
@@ -747,8 +747,8 @@ char * get_container_type(unsigned tindex)
* Arguments: [1] pointer to void [1] int
*
* Purpose: Sets SCSI inquiry data strings for vendor, product
* and revision level. Allows strings to be set in platform dependant
* files instead of in OS dependant driver source.
* and revision level. Allows strings to be set in platform dependent
* files instead of in OS dependent driver source.
*/
static void setinqstr(struct aac_dev *dev, void *data, int tindex)
drivers/scsi/aacraid/aacraid.h
+1 -1
View File
@@ -1259,7 +1259,7 @@ struct aac_dev
#define CACHE_UNSTABLE 2
/*
* Lets the client know at which level the data was commited on
* Lets the client know at which level the data was committed on
* a write request
*/
drivers/scsi/aacraid/commsup.c
+1 -1
View File
@@ -421,7 +421,7 @@ int aac_fib_send(u16 command, struct fib *fibptr, unsigned long size,
if (!(hw_fib->header.XferState & cpu_to_le32(HostOwned)))
return -EBUSY;
/*
* There are 5 cases with the wait and reponse requested flags.
* There are 5 cases with the wait and response requested flags.
* The only invalid cases are if the caller requests to wait and
* does not request a response and if the caller does not want a
* response and the Fib is not allocated from pool. If a response
drivers/scsi/advansys.c
+1 -1
View File
@@ -4544,7 +4544,7 @@ AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
* Copy 4 bytes to LRAM.
*
* The source data is assumed to be in little-endian order in memory
* and is maintained in little-endian order when writen to LRAM.
* and is maintained in little-endian order when written to LRAM.
*/
static void
AscMemDWordCopyPtrToLram(PortAddr iop_base,
drivers/scsi/aha1740.c
+1 -1
View File
@@ -461,7 +461,7 @@ static int aha1740_queuecommand_lck(Scsi_Cmnd * SCpnt, void (*done)(Scsi_Cmnd *)
/* The Adaptec Spec says the card is so fast that the loops
will only be executed once in the code below. Even if this
was true with the fastest processors when the spec was
written, it doesn't seem to be true with todays fast
written, it doesn't seem to be true with today's fast
processors. We print a warning if the code is executed more
often than LOOPCNT_WARN. If this happens, it should be
investigated. If the count reaches LOOPCNT_MAX, we assume
drivers/scsi/aic7xxx/aic79xx.h
+2 -2
View File
@@ -473,7 +473,7 @@ struct hardware_scb {
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
* or residual_sgptr does not have SG_LIST_NULL set.
*
* o We are transfering the last segment if residual_datacnt has
* o We are transferring the last segment if residual_datacnt has
* the SG_LAST_SEG flag set.
*
* Host:
@@ -516,7 +516,7 @@ struct hardware_scb {
*/
/*
* Definition of a scatter/gather element as transfered to the controller.
* Definition of a scatter/gather element as transferred to the controller.
* The aic7xxx chips only support a 24bit length. We use the top byte of
* the length to store additional address bits and a flag to indicate
* that a given segment terminates the transfer. This gives us an
drivers/scsi/aic7xxx/aic79xx.reg
+12 -12
View File
@@ -305,7 +305,7 @@ register HS_MAILBOX {
}
/*
* Sequencer Interupt Status
* Sequencer Interrupt Status
*/
register SEQINTSTAT {
address 0x00C
@@ -685,7 +685,7 @@ register DCHRXMSG0 {
}
/*
* CMC Recieve Message 0
* CMC Receive Message 0
*/
register CMCRXMSG0 {
address 0x090
@@ -696,7 +696,7 @@ register CMCRXMSG0 {
}
/*
* Overlay Recieve Message 0
* Overlay Receive Message 0
*/
register OVLYRXMSG0 {
address 0x090
@@ -732,7 +732,7 @@ register DCHRXMSG1 {
}
/*
* CMC Recieve Message 1
* CMC Receive Message 1
*/
register CMCRXMSG1 {
address 0x091
@@ -742,7 +742,7 @@ register CMCRXMSG1 {
}
/*
* Overlay Recieve Message 1
* Overlay Receive Message 1
*/
register OVLYRXMSG1 {
address 0x091
@@ -777,7 +777,7 @@ register DCHRXMSG2 {
}
/*
* CMC Recieve Message 2
* CMC Receive Message 2
*/
register CMCRXMSG2 {
address 0x092
@@ -787,7 +787,7 @@ register CMCRXMSG2 {
}
/*
* Overlay Recieve Message 2
* Overlay Receive Message 2
*/
register OVLYRXMSG2 {
address 0x092
@@ -816,7 +816,7 @@ register DCHRXMSG3 {
}
/*
* CMC Recieve Message 3
* CMC Receive Message 3
*/
register CMCRXMSG3 {
address 0x093
@@ -826,7 +826,7 @@ register CMCRXMSG3 {
}
/*
* Overlay Recieve Message 3
* Overlay Receive Message 3
*/
register OVLYRXMSG3 {
address 0x093
@@ -1249,7 +1249,7 @@ register TARGPCISTAT {
/*
* LQ Packet In
* The last LQ Packet recieved
* The last LQ Packet received
*/
register LQIN {
address 0x020
@@ -2573,7 +2573,7 @@ register IOPDNCTL {
}
/*
* Shaddow Host Address.
* Shadow Host Address.
*/
register SHADDR {
address 0x060
@@ -3983,7 +3983,7 @@ scratch_ram {
/*
* The maximum amount of time to wait, when interrupt coalescing
* is enabled, before issueing a CMDCMPLT interrupt for a completed
* is enabled, before issuing a CMDCMPLT interrupt for a completed
* command.
*/
INT_COALESCING_TIMER {
drivers/scsi/aic7xxx/aic79xx.seq
+9 -9
View File
@@ -567,7 +567,7 @@ BEGIN_CRITICAL;
shr SELOID, 4, SCB_SCSIID;
/*
* If we want to send a message to the device, ensure
* we are selecting with atn irregardless of our packetized
* we are selecting with atn regardless of our packetized
* agreement. Since SPI4 only allows target reset or PPR
* messages if this is a packetized connection, the change
* to our negotiation table entry for this selection will
@@ -960,7 +960,7 @@ p_status_okay:
* This is done to allow the host to send messages outside of an identify
* sequence while protecting the seqencer from testing the MK_MESSAGE bit
* on an SCB that might not be for the current nexus. (For example, a
* BDR message in responce to a bad reselection would leave us pointed to
* BDR message in response to a bad reselection would leave us pointed to
* an SCB that doesn't have anything to do with the current target).
*
* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
@@ -1507,7 +1507,7 @@ service_fifo:
* If the other FIFO needs loading, then it
* must not have claimed the S/G cache yet
* (SG_CACHE_AVAIL would have been cleared in
* the orginal FIFO mode and we test this above).
* the original FIFO mode and we test this above).
* Return to the idle loop so we can process the
* FIFO not currently on the bus first.
*/
@@ -1521,7 +1521,7 @@ idle_sgfetch_okay:
idle_sgfetch_start:
/*
* We fetch a "cacheline aligned" and sized amount of data
* so we don't end up referencing a non-existant page.
* so we don't end up referencing a non-existent page.
* Cacheline aligned is in quotes because the kernel will
* set the prefetch amount to a reasonable level if the
* cacheline size is unknown.
@@ -1551,7 +1551,7 @@ idle_sg_avail:
test DFSTATUS, PRELOAD_AVAIL jz return;
/*
* On the A, preloading a segment before HDMAENACK
* comes true can clobber the shaddow address of the
* comes true can clobber the shadow address of the
* first segment in the S/G FIFO. Wait until it is
* safe to proceed.
*/
@@ -2004,10 +2004,10 @@ pkt_handle_xfer:
* Defer handling of this NONPACKREQ until we
* can be sure it pertains to this FIFO. SAVEPTRS
* will not be asserted if the NONPACKREQ is for us,
* so we must simulate it if shaddow is valid. If
* shaddow is not valid, keep running this FIFO until we
* so we must simulate it if shadow is valid. If
* shadow is not valid, keep running this FIFO until we
* have satisfied the transfer by loading segments and
* waiting for either shaddow valid or last_seg_done.
* waiting for either shadow valid or last_seg_done.
*/
test MDFFSTAT, SHVALID jnz pkt_saveptrs;
pkt_service_fifo:
@@ -2171,7 +2171,7 @@ pkt_status_check_nonpackreq:
/*
* The unexpected nonpkt phase handler assumes that any
* data channel use will have a FIFO reference count. It
* turns out that the status handler doesn't need a refernce
* turns out that the status handler doesn't need a references
* count since the status received flag, and thus completion
* processing, cannot be set until the handler is finished.
* We increment the count here to make the nonpkt handler
drivers/scsi/aic7xxx/aic79xx_core.c
+12 -12
View File
@@ -562,7 +562,7 @@ ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
}
#endif
/*********************** Miscelaneous Support Functions ***********************/
/*********************** Miscellaneous Support Functions ***********************/
/*
* Return pointers to the transfer negotiation information
* for the specified our_id/remote_id pair.
@@ -599,7 +599,7 @@ void
ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
{
/*
* Write low byte first to accomodate registers
* Write low byte first to accommodate registers
* such as PRGMCNT where the order maters.
*/
ahd_outb(ahd, port, value & 0xFF);
@@ -2067,7 +2067,7 @@ ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
* that requires host assistance for completion.
* While handling the message phase(s), we will be
* notified by the sequencer after each byte is
* transfered so we can track bus phase changes.
* transferred so we can track bus phase changes.
*
* If this is the first time we've seen a HOST_MSG_LOOP
* interrupt, initialize the state of the host message
@@ -2487,7 +2487,7 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
/*
* Although the driver does not care about the
* 'Selection in Progress' status bit, the busy
* LED does. SELINGO is only cleared by a successfull
* LED does. SELINGO is only cleared by a successful
* selection, so we must manually clear it to insure
* the LED turns off just incase no future successful
* selections occur (e.g. no devices on the bus).
@@ -3548,7 +3548,7 @@ ahd_clear_critical_section(struct ahd_softc *ahd)
ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
ahd_outb(ahd, SIMODE1, simode1);
/*
* SCSIINT seems to glitch occassionally when
* SCSIINT seems to glitch occasionally when
* the interrupt masks are restored. Clear SCSIINT
* one more time so that only persistent errors
* are seen as a real interrupt.
@@ -3838,7 +3838,7 @@ ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
/*
* Update the bitmask of targets for which the controller should
* negotiate with at the next convenient oportunity. This currently
* negotiate with at the next convenient opportunity. This currently
* means the next time we send the initial identify messages for
* a new transaction.
*/
@@ -4200,7 +4200,7 @@ ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
/*
* During packetized transfers, the target will
* give us the oportunity to send command packets
* give us the opportunity to send command packets
* without us asserting attention.
*/
if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
@@ -5651,7 +5651,7 @@ ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
/*
* Requeue all tagged commands for this target
* currently in our posession so they can be
* currently in our possession so they can be
* converted to untagged commands.
*/
ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
@@ -6245,7 +6245,7 @@ ahd_shutdown(void *arg)
/*
* Reset the controller and record some information about it
* that is only available just after a reset. If "reinit" is
* non-zero, this reset occured after initial configuration
* non-zero, this reset occurred after initial configuration
* and the caller requests that the chip be fully reinitialized
* to a runable state. Chip interrupts are *not* enabled after
* a reinitialization. The caller must enable interrupts via
@@ -6495,7 +6495,7 @@ ahd_init_scbdata(struct ahd_softc *ahd)
}
/*
* Note that we were successfull
* Note that we were successful
*/
return (0);
@@ -7079,7 +7079,7 @@ ahd_init(struct ahd_softc *ahd)
return (ENOMEM);
/*
* Verify that the compiler hasn't over-agressively
* Verify that the compiler hasn't over-aggressively
* padded important structures.
*/
if (sizeof(struct hardware_scb) != 64)
@@ -10087,7 +10087,7 @@ ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
return (error);
/*
* Write the data. If we don't get throught the loop at
* Write the data. If we don't get through the loop at
* least once, the arguments were invalid.
*/
retval = EINVAL;
drivers/scsi/aic7xxx/aic79xx_osm.c
+1 -1
View File
@@ -1441,7 +1441,7 @@ ahd_platform_set_tags(struct ahd_softc *ahd, struct scsi_device *sdev,
usertags = ahd_linux_user_tagdepth(ahd, devinfo);
if (!was_queuing) {
/*
* Start out agressively and allow our
* Start out aggressively and allow our
* dynamic queue depth algorithm to take
* care of the rest.
*/
drivers/scsi/aic7xxx/aic7xxx.h
+2 -2
View File
@@ -440,7 +440,7 @@ struct hardware_scb {
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
* or residual_sgptr does not have SG_LIST_NULL set.
*
* o We are transfering the last segment if residual_datacnt has
* o We are transferring the last segment if residual_datacnt has
* the SG_LAST_SEG flag set.
*
* Host:
@@ -494,7 +494,7 @@ struct hardware_scb {
*/
/*
* Definition of a scatter/gather element as transfered to the controller.
* Definition of a scatter/gather element as transferred to the controller.
* The aic7xxx chips only support a 24bit length. We use the top byte of
* the length to store additional address bits and a flag to indicate
* that a given segment terminates the transfer. This gives us an
drivers/scsi/aic7xxx/aic7xxx.reg
+1 -1
View File
@@ -351,7 +351,7 @@ register SSTAT2 {
address 0x00d
access_mode RO
field OVERRUN 0x80
field SHVALID 0x40 /* Shaddow Layer non-zero */
field SHVALID 0x40 /* Shadow Layer non-zero */
field EXP_ACTIVE 0x10 /* SCSI Expander Active */
field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
drivers/scsi/aic7xxx/aic7xxx.seq
+5 -5
View File
@@ -57,10 +57,10 @@ PREFIX = "ahc_"
* a later time. This problem cannot be resolved by holding a single entry
* in scratch ram since a reconnecting target can request sense and this will
* create yet another SCB waiting for selection. The solution used here is to
* use byte 27 of the SCB as a psuedo-next pointer and to thread a list
* use byte 27 of the SCB as a pseudo-next pointer and to thread a list
* of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
* SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
* this list everytime a request sense occurs or after completing a non-tagged
* this list every time a request sense occurs or after completing a non-tagged
* command for which a second SCB has been queued. The sequencer will
* automatically consume the entries.
*/
@@ -752,7 +752,7 @@ idle_loop:
/*
* We fetch a "cacheline aligned" and sized amount of data
* so we don't end up referencing a non-existant page.
* so we don't end up referencing a non-existent page.
* Cacheline aligned is in quotes because the kernel will
* set the prefetch amount to a reasonable level if the
* cacheline size is unknown.
@@ -1485,7 +1485,7 @@ p_status_okay:
* This is done to allow the host to send messages outside of an identify
* sequence while protecting the seqencer from testing the MK_MESSAGE bit
* on an SCB that might not be for the current nexus. (For example, a
* BDR message in responce to a bad reselection would leave us pointed to
* BDR message in response to a bad reselection would leave us pointed to
* an SCB that doesn't have anything to do with the current target).
*
* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
@@ -1999,7 +1999,7 @@ if ((ahc->flags & AHC_TARGETROLE) != 0) {
* from out to in, wait an additional data release delay before continuing.
*/
change_phase:
/* Wait for preceeding I/O session to complete. */
/* Wait for preceding I/O session to complete. */
test SCSISIGI, ACKI jnz .;
/* Change the phase */
drivers/scsi/aic7xxx/aic7xxx_core.c
+9 -9
View File
@@ -427,7 +427,7 @@ ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
}
#endif
/*********************** Miscelaneous Support Functions ***********************/
/*********************** Miscellaneous Support Functions ***********************/
/*
* Determine whether the sequencer reported a residual
* for this SCB/transaction.
@@ -1243,7 +1243,7 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
* that requires host assistance for completion.
* While handling the message phase(s), we will be
* notified by the sequencer after each byte is
* transfered so we can track bus phase changes.
* transferred so we can track bus phase changes.
*
* If this is the first time we've seen a HOST_MSG_LOOP
* interrupt, initialize the state of the host message
@@ -1487,7 +1487,7 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
scbptr, ahc_inb(ahc, ARG_1),
ahc->scb_data->hscbs[scbptr].tag);
ahc_dump_card_state(ahc);
panic("for saftey");
panic("for safety");
break;
}
case OUT_OF_RANGE:
@@ -1733,7 +1733,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
/*
* Although the driver does not care about the
* 'Selection in Progress' status bit, the busy
* LED does. SELINGO is only cleared by a successfull
* LED does. SELINGO is only cleared by a successful
* selection, so we must manually clear it to insure
* the LED turns off just incase no future successful
* selections occur (e.g. no devices on the bus).
@@ -1943,7 +1943,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
if (lastphase != P_BUSFREE) {
/*
* Renegotiate with this device at the
* next oportunity just in case this busfree
* next opportunity just in case this busfree
* is due to a negotiation mismatch with the
* device.
*/
@@ -2442,7 +2442,7 @@ ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
/*
* Update the bitmask of targets for which the controller should
* negotiate with at the next convenient oportunity. This currently
* negotiate with at the next convenient opportunity. This currently
* means the next time we send the initial identify messages for
* a new transaction.
*/
@@ -4131,7 +4131,7 @@ ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
/*
* Requeue all tagged commands for this target
* currently in our posession so they can be
* currently in our possession so they can be
* converted to untagged commands.
*/
ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
@@ -4581,7 +4581,7 @@ ahc_shutdown(void *arg)
/*
* Reset the controller and record some information about it
* that is only available just after a reset. If "reinit" is
* non-zero, this reset occured after initial configuration
* non-zero, this reset occurred after initial configuration
* and the caller requests that the chip be fully reinitialized
* to a runable state. Chip interrupts are *not* enabled after
* a reinitialization. The caller must enable interrupts via
@@ -4899,7 +4899,7 @@ ahc_init_scbdata(struct ahc_softc *ahc)
ahc->next_queued_scb = ahc_get_scb(ahc);
/*
* Note that we were successfull
* Note that we were successful
*/
return (0);

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