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synced 2026-05-01 15:00:59 -07:00
Merge branch 'viafb-pll' into viafb-next
This commit is contained in:
Florian Tobias Schandinat
@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
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struct crt_mode_table *pDviTiming;
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unsigned long desirePixelClock, maxPixelClock;
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pDviTiming = mode->crtc;
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desirePixelClock = pDviTiming->clk / 1000000;
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desirePixelClock = pDviTiming->refresh_rate
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* pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
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/ 1000000;
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maxPixelClock = (unsigned long)viaparinfo->
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tmds_setting_info->max_pixel_clock;
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+352
-392
File diff suppressed because it is too large
Load Diff
@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
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/* VT3410 chipset*/
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#define VX900_FUNCTION3 0x3410
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#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
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struct IODATA {
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u8 Index;
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u8 Mask;
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@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
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int set_vres = plvds_setting_info->v_active;
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int panel_hres = plvds_setting_info->lcd_panel_hres;
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int panel_vres = plvds_setting_info->lcd_panel_vres;
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u32 pll_D_N;
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u32 pll_D_N, clock;
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struct display_timing mode_crt_reg, panel_crt_reg;
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struct crt_mode_table *panel_crt_table = NULL;
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struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
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@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
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DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
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if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
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viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
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plvds_setting_info->vclk = panel_crt_table->clk;
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clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
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* panel_crt_table->refresh_rate;
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plvds_setting_info->vclk = clock;
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if (set_iga == IGA1) {
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/* IGA1 doesn't have LCD scaling, so set it as centering. */
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viafb_load_crtc_timing(lcd_centering_timging
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@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
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fill_lcd_format();
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pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
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pll_D_N = viafb_get_clk_value(clock);
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DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
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viafb_set_vclock(pll_D_N, set_iga);
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lcd_patch_skew(plvds_setting_info, plvds_chip_info);
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@@ -627,77 +627,6 @@
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#define M2048x1536_R60_HSP NEGATIVE
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#define M2048x1536_R60_VSP POSITIVE
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/* define PLL index: */
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#define CLK_25_175M 25175000
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#define CLK_26_880M 26880000
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#define CLK_29_581M 29581000
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#define CLK_31_500M 31500000
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#define CLK_31_728M 31728000
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#define CLK_32_668M 32688000
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#define CLK_36_000M 36000000
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#define CLK_40_000M 40000000
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#define CLK_41_291M 41291000
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#define CLK_43_163M 43163000
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#define CLK_45_250M 45250000 /* 45.46MHz */
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#define CLK_46_000M 46000000
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#define CLK_46_996M 46996000
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#define CLK_48_000M 48000000
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#define CLK_48_875M 48875000
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#define CLK_49_500M 49500000
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#define CLK_52_406M 52406000
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#define CLK_52_977M 52977000
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#define CLK_56_250M 56250000
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#define CLK_57_275M 57275000
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#define CLK_60_466M 60466000
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#define CLK_61_500M 61500000
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#define CLK_65_000M 65000000
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#define CLK_65_178M 65178000
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#define CLK_66_750M 66750000 /* 67.116MHz */
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#define CLK_68_179M 68179000
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#define CLK_69_924M 69924000
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#define CLK_70_159M 70159000
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#define CLK_72_000M 72000000
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#define CLK_74_270M 74270000
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#define CLK_78_750M 78750000
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#define CLK_80_136M 80136000
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#define CLK_83_375M 83375000
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#define CLK_83_950M 83950000
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#define CLK_84_750M 84750000 /* 84.537Mhz */
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#define CLK_85_860M 85860000
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#define CLK_88_750M 88750000
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#define CLK_94_500M 94500000
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#define CLK_97_750M 97750000
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#define CLK_101_000M 101000000
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#define CLK_106_500M 106500000
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#define CLK_108_000M 108000000
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#define CLK_113_309M 113309000
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#define CLK_118_840M 118840000
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#define CLK_119_000M 119000000
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#define CLK_121_750M 121750000 /* 121.704MHz */
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#define CLK_125_104M 125104000
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#define CLK_135_000M 135000000
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#define CLK_136_700M 136700000
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#define CLK_138_400M 138400000
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#define CLK_146_760M 146760000
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#define CLK_148_500M 148500000
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#define CLK_153_920M 153920000
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#define CLK_156_000M 156000000
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#define CLK_157_500M 157500000
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#define CLK_162_000M 162000000
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#define CLK_187_000M 187000000
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#define CLK_193_295M 193295000
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#define CLK_202_500M 202500000
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#define CLK_204_000M 204000000
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#define CLK_218_500M 218500000
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#define CLK_234_000M 234000000
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#define CLK_267_250M 267250000
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#define CLK_297_500M 297500000
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#define CLK_74_481M 74481000
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#define CLK_172_798M 172798000
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#define CLK_122_614M 122614000
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/* Definition CRTC Timing Index */
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#define H_TOTAL_INDEX 0
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#define H_ADDR_INDEX 1
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@@ -722,76 +651,7 @@
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/* Definition Video Mode Pixel Clock (picoseconds)
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*/
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#define RES_480X640_60HZ_PIXCLOCK 39722
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#define RES_640X480_60HZ_PIXCLOCK 39722
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#define RES_640X480_75HZ_PIXCLOCK 31747
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#define RES_640X480_85HZ_PIXCLOCK 27777
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#define RES_640X480_100HZ_PIXCLOCK 23168
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#define RES_640X480_120HZ_PIXCLOCK 19081
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#define RES_720X480_60HZ_PIXCLOCK 37020
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#define RES_720X576_60HZ_PIXCLOCK 30611
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#define RES_800X600_60HZ_PIXCLOCK 25000
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#define RES_800X600_75HZ_PIXCLOCK 20203
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#define RES_800X600_85HZ_PIXCLOCK 17777
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#define RES_800X600_100HZ_PIXCLOCK 14667
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#define RES_800X600_120HZ_PIXCLOCK 11912
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#define RES_800X480_60HZ_PIXCLOCK 33805
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#define RES_848X480_60HZ_PIXCLOCK 31756
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#define RES_856X480_60HZ_PIXCLOCK 31518
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#define RES_1024X512_60HZ_PIXCLOCK 24218
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#define RES_1024X600_60HZ_PIXCLOCK 20460
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#define RES_1024X768_60HZ_PIXCLOCK 15385
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#define RES_1024X768_75HZ_PIXCLOCK 12699
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#define RES_1024X768_85HZ_PIXCLOCK 10582
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#define RES_1024X768_100HZ_PIXCLOCK 8825
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#define RES_1152X864_75HZ_PIXCLOCK 9259
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#define RES_1280X768_60HZ_PIXCLOCK 12480
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#define RES_1280X800_60HZ_PIXCLOCK 11994
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#define RES_1280X960_60HZ_PIXCLOCK 9259
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#define RES_1280X1024_60HZ_PIXCLOCK 9260
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#define RES_1280X1024_75HZ_PIXCLOCK 7408
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#define RES_1280X768_85HZ_PIXCLOCK 6349
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#define RES_1440X1050_60HZ_PIXCLOCK 7993
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#define RES_1600X1200_60HZ_PIXCLOCK 6172
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#define RES_1600X1200_75HZ_PIXCLOCK 4938
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#define RES_1280X720_60HZ_PIXCLOCK 13426
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#define RES_1200X900_60HZ_PIXCLOCK 17459
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#define RES_1920X1080_60HZ_PIXCLOCK 5787
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#define RES_1400X1050_60HZ_PIXCLOCK 8214
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#define RES_1400X1050_75HZ_PIXCLOCK 6410
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#define RES_1368X768_60HZ_PIXCLOCK 11647
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#define RES_960X600_60HZ_PIXCLOCK 22099
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#define RES_1000X600_60HZ_PIXCLOCK 20834
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#define RES_1024X576_60HZ_PIXCLOCK 21278
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#define RES_1088X612_60HZ_PIXCLOCK 18877
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#define RES_1152X720_60HZ_PIXCLOCK 14981
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#define RES_1200X720_60HZ_PIXCLOCK 14253
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#define RES_1280X600_60HZ_PIXCLOCK 16260
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#define RES_1280X720_50HZ_PIXCLOCK 16538
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#define RES_1280X768_50HZ_PIXCLOCK 15342
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#define RES_1366X768_50HZ_PIXCLOCK 14301
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#define RES_1366X768_60HZ_PIXCLOCK 11646
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#define RES_1360X768_60HZ_PIXCLOCK 11799
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#define RES_1440X900_60HZ_PIXCLOCK 9390
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#define RES_1440X900_75HZ_PIXCLOCK 7315
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#define RES_1600X900_60HZ_PIXCLOCK 8415
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#define RES_1600X1024_60HZ_PIXCLOCK 7315
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#define RES_1680X1050_60HZ_PIXCLOCK 6814
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#define RES_1680X1050_75HZ_PIXCLOCK 5348
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#define RES_1792X1344_60HZ_PIXCLOCK 4902
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#define RES_1856X1392_60HZ_PIXCLOCK 4577
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#define RES_1920X1200_60HZ_PIXCLOCK 5173
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#define RES_1920X1440_60HZ_PIXCLOCK 4274
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#define RES_1920X1440_75HZ_PIXCLOCK 3367
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#define RES_2048X1536_60HZ_PIXCLOCK 3742
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#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
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#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
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#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
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#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
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#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
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#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
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#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
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/* LCD display method
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*/
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@@ -822,7 +682,6 @@ struct display_timing {
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struct crt_mode_table {
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int refresh_rate;
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unsigned long clk;
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int h_sync_polarity;
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int v_sync_polarity;
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struct display_timing crtc;
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+121
-201
File diff suppressed because it is too large
Load Diff
@@ -41,14 +41,6 @@ struct patch_table {
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struct io_reg *io_reg_table;
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};
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struct res_map_refresh {
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int hres;
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int vres;
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int pixclock;
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int vmode_refresh;
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};
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extern int NUM_TOTAL_RES_MAP_REFRESH;
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extern int NUM_TOTAL_CEA_MODES;
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extern int NUM_TOTAL_CN400_ModeXregs;
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extern int NUM_TOTAL_CN700_ModeXregs;
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@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
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extern struct crt_mode_table CEAM1920x1080[];
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extern struct VideoModeTable CEA_HDMI_Modes[];
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extern struct res_map_refresh res_map_refresh_tbl[];
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extern struct io_reg CN400_ModeXregs[];
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extern struct io_reg CN700_ModeXregs[];
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extern struct io_reg KM400_ModeXregs[];
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