You've already forked linux-apfs
mirror of
https://github.com/linux-apfs/linux-apfs.git
synced 2026-05-01 15:00:59 -07:00
Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/paulus/ppc64-2.6
This commit is contained in:
Linus Torvalds
@@ -504,6 +504,13 @@ L: bonding-devel@lists.sourceforge.net
|
||||
W: http://sourceforge.net/projects/bonding/
|
||||
S: Supported
|
||||
|
||||
BROADBAND PROCESSOR ARCHITECTURE
|
||||
P: Arnd Bergmann
|
||||
M: arnd@arndb.de
|
||||
L: linuxppc64-dev@ozlabs.org
|
||||
W: http://linuxppc64.org
|
||||
S: Supported
|
||||
|
||||
BTTV VIDEO4LINUX DRIVER
|
||||
P: Gerd Knorr
|
||||
M: kraxel@bytesex.org
|
||||
|
||||
+20
-1
@@ -77,6 +77,10 @@ config PPC_PSERIES
|
||||
bool " IBM pSeries & new iSeries"
|
||||
default y
|
||||
|
||||
config PPC_BPA
|
||||
bool " Broadband Processor Architecture"
|
||||
depends on PPC_MULTIPLATFORM
|
||||
|
||||
config PPC_PMAC
|
||||
depends on PPC_MULTIPLATFORM
|
||||
bool " Apple G5 based machines"
|
||||
@@ -106,6 +110,21 @@ config PPC_OF
|
||||
bool
|
||||
default y
|
||||
|
||||
config XICS
|
||||
depends on PPC_PSERIES
|
||||
bool
|
||||
default y
|
||||
|
||||
config MPIC
|
||||
depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config BPA_IIC
|
||||
depends on PPC_BPA
|
||||
bool
|
||||
default y
|
||||
|
||||
# VMX is pSeries only for now until somebody writes the iSeries
|
||||
# exception vectors for it
|
||||
config ALTIVEC
|
||||
@@ -292,7 +311,7 @@ config MSCHUNKS
|
||||
|
||||
config PPC_RTAS
|
||||
bool
|
||||
depends on PPC_PSERIES
|
||||
depends on PPC_PSERIES || PPC_BPA
|
||||
default y
|
||||
|
||||
config RTAS_PROC
|
||||
|
||||
@@ -90,12 +90,14 @@ boot := arch/ppc64/boot
|
||||
boottarget-$(CONFIG_PPC_PSERIES) := zImage zImage.initrd
|
||||
boottarget-$(CONFIG_PPC_MAPLE) := zImage zImage.initrd
|
||||
boottarget-$(CONFIG_PPC_ISERIES) := vmlinux.sminitrd vmlinux.initrd vmlinux.sm
|
||||
boottarget-$(CONFIG_PPC_BPA) := zImage zImage.initrd
|
||||
$(boottarget-y): vmlinux
|
||||
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
|
||||
|
||||
bootimage-$(CONFIG_PPC_PSERIES) := $(boot)/zImage
|
||||
bootimage-$(CONFIG_PPC_PMAC) := vmlinux
|
||||
bootimage-$(CONFIG_PPC_MAPLE) := $(boot)/zImage
|
||||
bootimage-$(CONFIG_PPC_BPA) := zImage
|
||||
bootimage-$(CONFIG_PPC_ISERIES) := vmlinux
|
||||
BOOTIMAGE := $(bootimage-y)
|
||||
install: vmlinux
|
||||
|
||||
@@ -27,17 +27,21 @@ obj-$(CONFIG_PPC_ISERIES) += HvCall.o HvLpConfig.o LparData.o \
|
||||
mf.o HvLpEvent.o iSeries_proc.o iSeries_htab.o \
|
||||
iSeries_iommu.o
|
||||
|
||||
obj-$(CONFIG_PPC_MULTIPLATFORM) += nvram.o i8259.o prom_init.o prom.o mpic.o
|
||||
obj-$(CONFIG_PPC_MULTIPLATFORM) += nvram.o i8259.o prom_init.o prom.o
|
||||
|
||||
obj-$(CONFIG_PPC_PSERIES) += pSeries_pci.o pSeries_lpar.o pSeries_hvCall.o \
|
||||
pSeries_nvram.o rtasd.o ras.o pSeries_reconfig.o \
|
||||
xics.o rtas.o pSeries_setup.o pSeries_iommu.o
|
||||
pSeries_setup.o pSeries_iommu.o
|
||||
|
||||
obj-$(CONFIG_PPC_BPA) += bpa_setup.o bpa_iommu.o bpa_nvram.o \
|
||||
bpa_iic.o spider-pic.o
|
||||
|
||||
obj-$(CONFIG_EEH) += eeh.o
|
||||
obj-$(CONFIG_PROC_FS) += proc_ppc64.o
|
||||
obj-$(CONFIG_RTAS_FLASH) += rtas_flash.o
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o
|
||||
obj-$(CONFIG_PPC_RTAS) += rtas.o rtas_pci.o
|
||||
obj-$(CONFIG_RTAS_PROC) += rtas-proc.o
|
||||
obj-$(CONFIG_SCANLOG) += scanlog.o
|
||||
obj-$(CONFIG_VIOPATH) += viopath.o
|
||||
@@ -46,6 +50,8 @@ obj-$(CONFIG_HVC_CONSOLE) += hvconsole.o
|
||||
obj-$(CONFIG_BOOTX_TEXT) += btext.o
|
||||
obj-$(CONFIG_HVCS) += hvcserver.o
|
||||
obj-$(CONFIG_IBMVIO) += vio.o
|
||||
obj-$(CONFIG_XICS) += xics.o
|
||||
obj-$(CONFIG_MPIC) += mpic.o
|
||||
|
||||
obj-$(CONFIG_PPC_PMAC) += pmac_setup.o pmac_feature.o pmac_pci.o \
|
||||
pmac_time.o pmac_nvram.o pmac_low_i2c.o
|
||||
@@ -58,6 +64,7 @@ ifdef CONFIG_SMP
|
||||
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o smp-tbsync.o
|
||||
obj-$(CONFIG_PPC_ISERIES) += iSeries_smp.o
|
||||
obj-$(CONFIG_PPC_PSERIES) += pSeries_smp.o
|
||||
obj-$(CONFIG_PPC_BPA) += pSeries_smp.o
|
||||
obj-$(CONFIG_PPC_MAPLE) += smp-tbsync.o
|
||||
endif
|
||||
|
||||
|
||||
@@ -0,0 +1,270 @@
|
||||
/*
|
||||
* BPA Internal Interrupt Controller
|
||||
*
|
||||
* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
|
||||
*
|
||||
* Author: Arnd Bergmann <arndb@de.ibm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
#include "bpa_iic.h"
|
||||
|
||||
struct iic_pending_bits {
|
||||
u32 data;
|
||||
u8 flags;
|
||||
u8 class;
|
||||
u8 source;
|
||||
u8 prio;
|
||||
};
|
||||
|
||||
enum iic_pending_flags {
|
||||
IIC_VALID = 0x80,
|
||||
IIC_IPI = 0x40,
|
||||
};
|
||||
|
||||
struct iic_regs {
|
||||
struct iic_pending_bits pending;
|
||||
struct iic_pending_bits pending_destr;
|
||||
u64 generate;
|
||||
u64 prio;
|
||||
};
|
||||
|
||||
struct iic {
|
||||
struct iic_regs __iomem *regs;
|
||||
};
|
||||
|
||||
static DEFINE_PER_CPU(struct iic, iic);
|
||||
|
||||
void iic_local_enable(void)
|
||||
{
|
||||
out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
|
||||
}
|
||||
|
||||
void iic_local_disable(void)
|
||||
{
|
||||
out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
|
||||
}
|
||||
|
||||
static unsigned int iic_startup(unsigned int irq)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void iic_enable(unsigned int irq)
|
||||
{
|
||||
iic_local_enable();
|
||||
}
|
||||
|
||||
static void iic_disable(unsigned int irq)
|
||||
{
|
||||
}
|
||||
|
||||
static void iic_end(unsigned int irq)
|
||||
{
|
||||
iic_local_enable();
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type iic_pic = {
|
||||
.typename = " BPA-IIC ",
|
||||
.startup = iic_startup,
|
||||
.enable = iic_enable,
|
||||
.disable = iic_disable,
|
||||
.end = iic_end,
|
||||
};
|
||||
|
||||
static int iic_external_get_irq(struct iic_pending_bits pending)
|
||||
{
|
||||
int irq;
|
||||
unsigned char node, unit;
|
||||
|
||||
node = pending.source >> 4;
|
||||
unit = pending.source & 0xf;
|
||||
irq = -1;
|
||||
|
||||
/*
|
||||
* This mapping is specific to the Broadband
|
||||
* Engine. We might need to get the numbers
|
||||
* from the device tree to support future CPUs.
|
||||
*/
|
||||
switch (unit) {
|
||||
case 0x00:
|
||||
case 0x0b:
|
||||
/*
|
||||
* One of these units can be connected
|
||||
* to an external interrupt controller.
|
||||
*/
|
||||
if (pending.prio > 0x3f ||
|
||||
pending.class != 2)
|
||||
break;
|
||||
irq = IIC_EXT_OFFSET
|
||||
+ spider_get_irq(pending.prio + node * IIC_NODE_STRIDE)
|
||||
+ node * IIC_NODE_STRIDE;
|
||||
break;
|
||||
case 0x01 ... 0x04:
|
||||
case 0x07 ... 0x0a:
|
||||
/*
|
||||
* These units are connected to the SPEs
|
||||
*/
|
||||
if (pending.class > 2)
|
||||
break;
|
||||
irq = IIC_SPE_OFFSET
|
||||
+ pending.class * IIC_CLASS_STRIDE
|
||||
+ node * IIC_NODE_STRIDE
|
||||
+ unit;
|
||||
break;
|
||||
}
|
||||
if (irq == -1)
|
||||
printk(KERN_WARNING "Unexpected interrupt class %02x, "
|
||||
"source %02x, prio %02x, cpu %02x\n", pending.class,
|
||||
pending.source, pending.prio, smp_processor_id());
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* Get an IRQ number from the pending state register of the IIC */
|
||||
int iic_get_irq(struct pt_regs *regs)
|
||||
{
|
||||
struct iic *iic;
|
||||
int irq;
|
||||
struct iic_pending_bits pending;
|
||||
|
||||
iic = &__get_cpu_var(iic);
|
||||
*(unsigned long *) &pending =
|
||||
in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
|
||||
|
||||
irq = -1;
|
||||
if (pending.flags & IIC_VALID) {
|
||||
if (pending.flags & IIC_IPI) {
|
||||
irq = IIC_IPI_OFFSET + (pending.prio >> 4);
|
||||
/*
|
||||
if (irq > 0x80)
|
||||
printk(KERN_WARNING "Unexpected IPI prio %02x"
|
||||
"on CPU %02x\n", pending.prio,
|
||||
smp_processor_id());
|
||||
*/
|
||||
} else {
|
||||
irq = iic_external_get_irq(pending);
|
||||
}
|
||||
}
|
||||
return irq;
|
||||
}
|
||||
|
||||
static struct iic_regs __iomem *find_iic(int cpu)
|
||||
{
|
||||
struct device_node *np;
|
||||
int nodeid = cpu / 2;
|
||||
unsigned long regs;
|
||||
struct iic_regs __iomem *iic_regs;
|
||||
|
||||
for (np = of_find_node_by_type(NULL, "cpu");
|
||||
np;
|
||||
np = of_find_node_by_type(np, "cpu")) {
|
||||
if (nodeid == *(int *)get_property(np, "node-id", NULL))
|
||||
break;
|
||||
}
|
||||
|
||||
if (!np) {
|
||||
printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
|
||||
iic_regs = NULL;
|
||||
} else {
|
||||
regs = *(long *)get_property(np, "iic", NULL);
|
||||
|
||||
/* hack until we have decided on the devtree info */
|
||||
regs += 0x400;
|
||||
if (cpu & 1)
|
||||
regs += 0x20;
|
||||
|
||||
printk(KERN_DEBUG "IIC for CPU %d at %lx\n", cpu, regs);
|
||||
iic_regs = __ioremap(regs, sizeof(struct iic_regs),
|
||||
_PAGE_NO_CACHE);
|
||||
}
|
||||
return iic_regs;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void iic_setup_cpu(void)
|
||||
{
|
||||
out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
|
||||
}
|
||||
|
||||
void iic_cause_IPI(int cpu, int mesg)
|
||||
{
|
||||
out_be64(&per_cpu(iic, cpu).regs->generate, mesg);
|
||||
}
|
||||
|
||||
static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
|
||||
smp_message_recv(irq - IIC_IPI_OFFSET, regs);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void iic_request_ipi(int irq, const char *name)
|
||||
{
|
||||
/* IPIs are marked SA_INTERRUPT as they must run with irqs
|
||||
* disabled */
|
||||
get_irq_desc(irq)->handler = &iic_pic;
|
||||
get_irq_desc(irq)->status |= IRQ_PER_CPU;
|
||||
request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL);
|
||||
}
|
||||
|
||||
void iic_request_IPIs(void)
|
||||
{
|
||||
iic_request_ipi(IIC_IPI_OFFSET + PPC_MSG_CALL_FUNCTION, "IPI-call");
|
||||
iic_request_ipi(IIC_IPI_OFFSET + PPC_MSG_RESCHEDULE, "IPI-resched");
|
||||
#ifdef CONFIG_DEBUGGER
|
||||
iic_request_ipi(IIC_IPI_OFFSET + PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
|
||||
#endif /* CONFIG_DEBUGGER */
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
static void iic_setup_spe_handlers(void)
|
||||
{
|
||||
int be, isrc;
|
||||
|
||||
/* Assume two threads per BE are present */
|
||||
for (be=0; be < num_present_cpus() / 2; be++) {
|
||||
for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
|
||||
int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
|
||||
get_irq_desc(irq)->handler = &iic_pic;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void iic_init_IRQ(void)
|
||||
{
|
||||
int cpu, irq_offset;
|
||||
struct iic *iic;
|
||||
|
||||
irq_offset = 0;
|
||||
for_each_cpu(cpu) {
|
||||
iic = &per_cpu(iic, cpu);
|
||||
iic->regs = find_iic(cpu);
|
||||
if (iic->regs)
|
||||
out_be64(&iic->regs->prio, 0xff);
|
||||
}
|
||||
iic_setup_spe_handlers();
|
||||
}
|
||||
@@ -0,0 +1,62 @@
|
||||
#ifndef ASM_BPA_IIC_H
|
||||
#define ASM_BPA_IIC_H
|
||||
#ifdef __KERNEL__
|
||||
/*
|
||||
* Mapping of IIC pending bits into per-node
|
||||
* interrupt numbers.
|
||||
*
|
||||
* IRQ FF CC SS PP FF CC SS PP Description
|
||||
*
|
||||
* 00-3f 80 02 +0 00 - 80 02 +0 3f South Bridge
|
||||
* 00-3f 80 02 +b 00 - 80 02 +b 3f South Bridge
|
||||
* 41-4a 80 00 +1 ** - 80 00 +a ** SPU Class 0
|
||||
* 51-5a 80 01 +1 ** - 80 01 +a ** SPU Class 1
|
||||
* 61-6a 80 02 +1 ** - 80 02 +a ** SPU Class 2
|
||||
* 70-7f C0 ** ** 00 - C0 ** ** 0f IPI
|
||||
*
|
||||
* F flags
|
||||
* C class
|
||||
* S source
|
||||
* P Priority
|
||||
* + node number
|
||||
* * don't care
|
||||
*
|
||||
* A node consists of a Broadband Engine and an optional
|
||||
* south bridge device providing a maximum of 64 IRQs.
|
||||
* The south bridge may be connected to either IOIF0
|
||||
* or IOIF1.
|
||||
* Each SPE is represented as three IRQ lines, one per
|
||||
* interrupt class.
|
||||
* 16 IRQ numbers are reserved for inter processor
|
||||
* interruptions, although these are only used in the
|
||||
* range of the first node.
|
||||
*
|
||||
* This scheme needs 128 IRQ numbers per BIF node ID,
|
||||
* which means that with the total of 512 lines
|
||||
* available, we can have a maximum of four nodes.
|
||||
*/
|
||||
|
||||
enum {
|
||||
IIC_EXT_OFFSET = 0x00, /* Start of south bridge IRQs */
|
||||
IIC_NUM_EXT = 0x40, /* Number of south bridge IRQs */
|
||||
IIC_SPE_OFFSET = 0x40, /* Start of SPE interrupts */
|
||||
IIC_CLASS_STRIDE = 0x10, /* SPE IRQs per class */
|
||||
IIC_IPI_OFFSET = 0x70, /* Start of IPI IRQs */
|
||||
IIC_NUM_IPIS = 0x10, /* IRQs reserved for IPI */
|
||||
IIC_NODE_STRIDE = 0x80, /* Total IRQs per node */
|
||||
};
|
||||
|
||||
extern void iic_init_IRQ(void);
|
||||
extern int iic_get_irq(struct pt_regs *regs);
|
||||
extern void iic_cause_IPI(int cpu, int mesg);
|
||||
extern void iic_request_IPIs(void);
|
||||
extern void iic_setup_cpu(void);
|
||||
extern void iic_local_enable(void);
|
||||
extern void iic_local_disable(void);
|
||||
|
||||
|
||||
extern void spider_init_IRQ(void);
|
||||
extern int spider_get_irq(unsigned long int_pending);
|
||||
|
||||
#endif
|
||||
#endif /* ASM_BPA_IIC_H */
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* IOMMU implementation for Broadband Processor Architecture
|
||||
* We just establish a linear mapping at boot by setting all the
|
||||
* IOPT cache entries in the CPU.
|
||||
* The mapping functions should be identical to pci_direct_iommu,
|
||||
* except for the handling of the high order bit that is required
|
||||
* by the Spider bridge. These should be split into a separate
|
||||
* file at the point where we get a different bridge chip.
|
||||
*
|
||||
* Copyright (C) 2005 IBM Deutschland Entwicklung GmbH,
|
||||
* Arnd Bergmann <arndb@de.ibm.com>
|
||||
*
|
||||
* Based on linear mapping
|
||||
* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/sections.h>
|
||||
#include <asm/iommu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pmac_feature.h>
|
||||
#include <asm/abs_addr.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
#include "pci.h"
|
||||
#include "bpa_iommu.h"
|
||||
|
||||
static inline unsigned long
|
||||
get_iopt_entry(unsigned long real_address, unsigned long ioid,
|
||||
unsigned long prot)
|
||||
{
|
||||
return (prot & IOPT_PROT_MASK)
|
||||
| (IOPT_COHERENT)
|
||||
| (IOPT_ORDER_VC)
|
||||
| (real_address & IOPT_RPN_MASK)
|
||||
| (ioid & IOPT_IOID_MASK);
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
unsigned long val;
|
||||
} ioste;
|
||||
|
||||
static inline ioste
|
||||
mk_ioste(unsigned long val)
|
||||
{
|
||||
ioste ioste = { .val = val, };
|
||||
return ioste;
|
||||
}
|
||||
|
||||
static inline ioste
|
||||
get_iost_entry(unsigned long iopt_base, unsigned long io_address, unsigned page_size)
|
||||
{
|
||||
unsigned long ps;
|
||||
unsigned long iostep;
|
||||
unsigned long nnpt;
|
||||
unsigned long shift;
|
||||
|
||||
switch (page_size) {
|
||||
case 0x1000000:
|
||||
ps = IOST_PS_16M;
|
||||
nnpt = 0; /* one page per segment */
|
||||
shift = 5; /* segment has 16 iopt entries */
|
||||
break;
|
||||
|
||||
case 0x100000:
|
||||
ps = IOST_PS_1M;
|
||||
nnpt = 0; /* one page per segment */
|
||||
shift = 1; /* segment has 256 iopt entries */
|
||||
break;
|
||||
|
||||
case 0x10000:
|
||||
ps = IOST_PS_64K;
|
||||
nnpt = 0x07; /* 8 pages per io page table */
|
||||
shift = 0; /* all entries are used */
|
||||
break;
|
||||
|
||||
case 0x1000:
|
||||
ps = IOST_PS_4K;
|
||||
nnpt = 0x7f; /* 128 pages per io page table */
|
||||
shift = 0; /* all entries are used */
|
||||
break;
|
||||
|
||||
default: /* not a known compile time constant */
|
||||
BUILD_BUG_ON(1);
|
||||
break;
|
||||
}
|
||||
|
||||
iostep = iopt_base +
|
||||
/* need 8 bytes per iopte */
|
||||
(((io_address / page_size * 8)
|
||||
/* align io page tables on 4k page boundaries */
|
||||
<< shift)
|
||||
/* nnpt+1 pages go into each iopt */
|
||||
& ~(nnpt << 12));
|
||||
|
||||
nnpt++; /* this seems to work, but the documentation is not clear
|
||||
about wether we put nnpt or nnpt-1 into the ioste bits.
|
||||
In theory, this can't work for 4k pages. */
|
||||
return mk_ioste(IOST_VALID_MASK
|
||||
| (iostep & IOST_PT_BASE_MASK)
|
||||
| ((nnpt << 5) & IOST_NNPT_MASK)
|
||||
| (ps & IOST_PS_MASK));
|
||||
}
|
||||
|
||||
/* compute the address of an io pte */
|
||||
static inline unsigned long
|
||||
get_ioptep(ioste iost_entry, unsigned long io_address)
|
||||
{
|
||||
unsigned long iopt_base;
|
||||
unsigned long page_size;
|
||||
unsigned long page_number;
|
||||
unsigned long iopt_offset;
|
||||
|
||||
iopt_base = iost_entry.val & IOST_PT_BASE_MASK;
|
||||
page_size = iost_entry.val & IOST_PS_MASK;
|
||||
|
||||
/* decode page size to compute page number */
|
||||
page_number = (io_address & 0x0fffffff) >> (10 + 2 * page_size);
|
||||
/* page number is an offset into the io page table */
|
||||
iopt_offset = (page_number << 3) & 0x7fff8ul;
|
||||
return iopt_base + iopt_offset;
|
||||
}
|
||||
|
||||
/* compute the tag field of the iopt cache entry */
|
||||
static inline unsigned long
|
||||
get_ioc_tag(ioste iost_entry, unsigned long io_address)
|
||||
{
|
||||
unsigned long iopte = get_ioptep(iost_entry, io_address);
|
||||
|
||||
return IOPT_VALID_MASK
|
||||
| ((iopte & 0x00000000000000ff8ul) >> 3)
|
||||
| ((iopte & 0x0000003fffffc0000ul) >> 9);
|
||||
}
|
||||
|
||||
/* compute the hashed 6 bit index for the 4-way associative pte cache */
|
||||
static inline unsigned long
|
||||
get_ioc_hash(ioste iost_entry, unsigned long io_address)
|
||||
{
|
||||
unsigned long iopte = get_ioptep(iost_entry, io_address);
|
||||
|
||||
return ((iopte & 0x000000000000001f8ul) >> 3)
|
||||
^ ((iopte & 0x00000000000020000ul) >> 17)
|
||||
^ ((iopte & 0x00000000000010000ul) >> 15)
|
||||
^ ((iopte & 0x00000000000008000ul) >> 13)
|
||||
^ ((iopte & 0x00000000000004000ul) >> 11)
|
||||
^ ((iopte & 0x00000000000002000ul) >> 9)
|
||||
^ ((iopte & 0x00000000000001000ul) >> 7);
|
||||
}
|
||||
|
||||
/* same as above, but pretend that we have a simpler 1-way associative
|
||||
pte cache with an 8 bit index */
|
||||
static inline unsigned long
|
||||
get_ioc_hash_1way(ioste iost_entry, unsigned long io_address)
|
||||
{
|
||||
unsigned long iopte = get_ioptep(iost_entry, io_address);
|
||||
|
||||
return ((iopte & 0x000000000000001f8ul) >> 3)
|
||||
^ ((iopte & 0x00000000000020000ul) >> 17)
|
||||
^ ((iopte & 0x00000000000010000ul) >> 15)
|
||||
^ ((iopte & 0x00000000000008000ul) >> 13)
|
||||
^ ((iopte & 0x00000000000004000ul) >> 11)
|
||||
^ ((iopte & 0x00000000000002000ul) >> 9)
|
||||
^ ((iopte & 0x00000000000001000ul) >> 7)
|
||||
^ ((iopte & 0x0000000000000c000ul) >> 8);
|
||||
}
|
||||
|
||||
static inline ioste
|
||||
get_iost_cache(void __iomem *base, unsigned long index)
|
||||
{
|
||||
unsigned long __iomem *p = (base + IOC_ST_CACHE_DIR);
|
||||
return mk_ioste(in_be64(&p[index]));
|
||||
}
|
||||
|
||||
static inline void
|
||||
set_iost_cache(void __iomem *base, unsigned long index, ioste ste)
|
||||
{
|
||||
unsigned long __iomem *p = (base + IOC_ST_CACHE_DIR);
|
||||
pr_debug("ioste %02lx was %016lx, store %016lx", index,
|
||||
get_iost_cache(base, index).val, ste.val);
|
||||
out_be64(&p[index], ste.val);
|
||||
pr_debug(" now %016lx\n", get_iost_cache(base, index).val);
|
||||
}
|
||||
|
||||
static inline unsigned long
|
||||
get_iopt_cache(void __iomem *base, unsigned long index, unsigned long *tag)
|
||||
{
|
||||
unsigned long __iomem *tags = (void *)(base + IOC_PT_CACHE_DIR);
|
||||
unsigned long __iomem *p = (void *)(base + IOC_PT_CACHE_REG);
|
||||
|
||||
*tag = tags[index];
|
||||
rmb();
|
||||
return *p;
|
||||
}
|
||||
|
||||
static inline void
|
||||
set_iopt_cache(void __iomem *base, unsigned long index,
|
||||
unsigned long tag, unsigned long val)
|
||||
{
|
||||
unsigned long __iomem *tags = base + IOC_PT_CACHE_DIR;
|
||||
unsigned long __iomem *p = base + IOC_PT_CACHE_REG;
|
||||
pr_debug("iopt %02lx was v%016lx/t%016lx, store v%016lx/t%016lx\n",
|
||||
index, get_iopt_cache(base, index, &oldtag), oldtag, val, tag);
|
||||
|
||||
out_be64(p, val);
|
||||
out_be64(&tags[index], tag);
|
||||
}
|
||||
|
||||
static inline void
|
||||
set_iost_origin(void __iomem *base)
|
||||
{
|
||||
unsigned long __iomem *p = base + IOC_ST_ORIGIN;
|
||||
unsigned long origin = IOSTO_ENABLE | IOSTO_SW;
|
||||
|
||||
pr_debug("iost_origin %016lx, now %016lx\n", in_be64(p), origin);
|
||||
out_be64(p, origin);
|
||||
}
|
||||
|
||||
static inline void
|
||||
set_iocmd_config(void __iomem *base)
|
||||
{
|
||||
unsigned long __iomem *p = base + 0xc00;
|
||||
unsigned long conf;
|
||||
|
||||
conf = in_be64(p);
|
||||
pr_debug("iost_conf %016lx, now %016lx\n", conf, conf | IOCMD_CONF_TE);
|
||||
out_be64(p, conf | IOCMD_CONF_TE);
|
||||
}
|
||||
|
||||
/* FIXME: get these from the device tree */
|
||||
#define ioc_base 0x20000511000ull
|
||||
#define ioc_mmio_base 0x20000510000ull
|
||||
#define ioid 0x48a
|
||||
#define iopt_phys_offset (- 0x20000000) /* We have a 512MB offset from the SB */
|
||||
#define io_page_size 0x1000000
|
||||
|
||||
static unsigned long map_iopt_entry(unsigned long address)
|
||||
{
|
||||
switch (address >> 20) {
|
||||
case 0x600:
|
||||
address = 0x24020000000ull; /* spider i/o */
|
||||
break;
|
||||
default:
|
||||
address += iopt_phys_offset;
|
||||
break;
|
||||
}
|
||||
|
||||
return get_iopt_entry(address, ioid, IOPT_PROT_RW);
|
||||
}
|
||||
|
||||
static void iommu_bus_setup_null(struct pci_bus *b) { }
|
||||
static void iommu_dev_setup_null(struct pci_dev *d) { }
|
||||
|
||||
/* initialize the iommu to support a simple linear mapping
|
||||
* for each DMA window used by any device. For now, we
|
||||
* happen to know that there is only one DMA window in use,
|
||||
* starting at iopt_phys_offset. */
|
||||
static void bpa_map_iommu(void)
|
||||
{
|
||||
unsigned long address;
|
||||
void __iomem *base;
|
||||
ioste ioste;
|
||||
unsigned long index;
|
||||
|
||||
base = __ioremap(ioc_base, 0x1000, _PAGE_NO_CACHE);
|
||||
pr_debug("%lx mapped to %p\n", ioc_base, base);
|
||||
set_iocmd_config(base);
|
||||
iounmap(base);
|
||||
|
||||
base = __ioremap(ioc_mmio_base, 0x1000, _PAGE_NO_CACHE);
|
||||
pr_debug("%lx mapped to %p\n", ioc_mmio_base, base);
|
||||
|
||||
set_iost_origin(base);
|
||||
|
||||
for (address = 0; address < 0x100000000ul; address += io_page_size) {
|
||||
ioste = get_iost_entry(0x10000000000ul, address, io_page_size);
|
||||
if ((address & 0xfffffff) == 0) /* segment start */
|
||||
set_iost_cache(base, address >> 28, ioste);
|
||||
index = get_ioc_hash_1way(ioste, address);
|
||||
pr_debug("addr %08lx, index %02lx, ioste %016lx\n",
|
||||
address, index, ioste.val);
|
||||
set_iopt_cache(base,
|
||||
get_ioc_hash_1way(ioste, address),
|
||||
get_ioc_tag(ioste, address),
|
||||
map_iopt_entry(address));
|
||||
}
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
|
||||
static void *bpa_alloc_coherent(struct device *hwdev, size_t size,
|
||||
dma_addr_t *dma_handle, unsigned int __nocast flag)
|
||||
{
|
||||
void *ret;
|
||||
|
||||
ret = (void *)__get_free_pages(flag, get_order(size));
|
||||
if (ret != NULL) {
|
||||
memset(ret, 0, size);
|
||||
*dma_handle = virt_to_abs(ret) | BPA_DMA_VALID;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void bpa_free_coherent(struct device *hwdev, size_t size,
|
||||
void *vaddr, dma_addr_t dma_handle)
|
||||
{
|
||||
free_pages((unsigned long)vaddr, get_order(size));
|
||||
}
|
||||
|
||||
static dma_addr_t bpa_map_single(struct device *hwdev, void *ptr,
|
||||
size_t size, enum dma_data_direction direction)
|
||||
{
|
||||
return virt_to_abs(ptr) | BPA_DMA_VALID;
|
||||
}
|
||||
|
||||
static void bpa_unmap_single(struct device *hwdev, dma_addr_t dma_addr,
|
||||
size_t size, enum dma_data_direction direction)
|
||||
{
|
||||
}
|
||||
|
||||
static int bpa_map_sg(struct device *hwdev, struct scatterlist *sg,
|
||||
int nents, enum dma_data_direction direction)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nents; i++, sg++) {
|
||||
sg->dma_address = (page_to_phys(sg->page) + sg->offset)
|
||||
| BPA_DMA_VALID;
|
||||
sg->dma_length = sg->length;
|
||||
}
|
||||
|
||||
return nents;
|
||||
}
|
||||
|
||||
static void bpa_unmap_sg(struct device *hwdev, struct scatterlist *sg,
|
||||
int nents, enum dma_data_direction direction)
|
||||
{
|
||||
}
|
||||
|
||||
static int bpa_dma_supported(struct device *dev, u64 mask)
|
||||
{
|
||||
return mask < 0x100000000ull;
|
||||
}
|
||||
|
||||
void bpa_init_iommu(void)
|
||||
{
|
||||
bpa_map_iommu();
|
||||
|
||||
/* Direct I/O, IOMMU off */
|
||||
ppc_md.iommu_dev_setup = iommu_dev_setup_null;
|
||||
ppc_md.iommu_bus_setup = iommu_bus_setup_null;
|
||||
|
||||
pci_dma_ops.alloc_coherent = bpa_alloc_coherent;
|
||||
pci_dma_ops.free_coherent = bpa_free_coherent;
|
||||
pci_dma_ops.map_single = bpa_map_single;
|
||||
pci_dma_ops.unmap_single = bpa_unmap_single;
|
||||
pci_dma_ops.map_sg = bpa_map_sg;
|
||||
pci_dma_ops.unmap_sg = bpa_unmap_sg;
|
||||
pci_dma_ops.dma_supported = bpa_dma_supported;
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
#ifndef BPA_IOMMU_H
|
||||
#define BPA_IOMMU_H
|
||||
|
||||
/* some constants */
|
||||
enum {
|
||||
/* segment table entries */
|
||||
IOST_VALID_MASK = 0x8000000000000000ul,
|
||||
IOST_TAG_MASK = 0x3000000000000000ul,
|
||||
IOST_PT_BASE_MASK = 0x000003fffffff000ul,
|
||||
IOST_NNPT_MASK = 0x0000000000000fe0ul,
|
||||
IOST_PS_MASK = 0x000000000000000ful,
|
||||
|
||||
IOST_PS_4K = 0x1,
|
||||
IOST_PS_64K = 0x3,
|
||||
IOST_PS_1M = 0x5,
|
||||
IOST_PS_16M = 0x7,
|
||||
|
||||
/* iopt tag register */
|
||||
IOPT_VALID_MASK = 0x0000000200000000ul,
|
||||
IOPT_TAG_MASK = 0x00000001fffffffful,
|
||||
|
||||
/* iopt cache register */
|
||||
IOPT_PROT_MASK = 0xc000000000000000ul,
|
||||
IOPT_PROT_NONE = 0x0000000000000000ul,
|
||||
IOPT_PROT_READ = 0x4000000000000000ul,
|
||||
IOPT_PROT_WRITE = 0x8000000000000000ul,
|
||||
IOPT_PROT_RW = 0xc000000000000000ul,
|
||||
IOPT_COHERENT = 0x2000000000000000ul,
|
||||
|
||||
IOPT_ORDER_MASK = 0x1800000000000000ul,
|
||||
/* order access to same IOID/VC on same address */
|
||||
IOPT_ORDER_ADDR = 0x0800000000000000ul,
|
||||
/* similar, but only after a write access */
|
||||
IOPT_ORDER_WRITES = 0x1000000000000000ul,
|
||||
/* Order all accesses to same IOID/VC */
|
||||
IOPT_ORDER_VC = 0x1800000000000000ul,
|
||||
|
||||
IOPT_RPN_MASK = 0x000003fffffff000ul,
|
||||
IOPT_HINT_MASK = 0x0000000000000800ul,
|
||||
IOPT_IOID_MASK = 0x00000000000007fful,
|
||||
|
||||
IOSTO_ENABLE = 0x8000000000000000ul,
|
||||
IOSTO_ORIGIN = 0x000003fffffff000ul,
|
||||
IOSTO_HW = 0x0000000000000800ul,
|
||||
IOSTO_SW = 0x0000000000000400ul,
|
||||
|
||||
IOCMD_CONF_TE = 0x0000800000000000ul,
|
||||
|
||||
/* memory mapped registers */
|
||||
IOC_PT_CACHE_DIR = 0x000,
|
||||
IOC_ST_CACHE_DIR = 0x800,
|
||||
IOC_PT_CACHE_REG = 0x910,
|
||||
IOC_ST_ORIGIN = 0x918,
|
||||
IOC_CONF = 0x930,
|
||||
|
||||
/* The high bit needs to be set on every DMA address,
|
||||
only 2GB are addressable */
|
||||
BPA_DMA_VALID = 0x80000000,
|
||||
BPA_DMA_MASK = 0x7fffffff,
|
||||
};
|
||||
|
||||
|
||||
void bpa_init_iommu(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* NVRAM for CPBW
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2005
|
||||
*
|
||||
* Authors : Utz Bacher <utz.bacher@de.ibm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/nvram.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
static void __iomem *bpa_nvram_start;
|
||||
static long bpa_nvram_len;
|
||||
static spinlock_t bpa_nvram_lock = SPIN_LOCK_UNLOCKED;
|
||||
|
||||
static ssize_t bpa_nvram_read(char *buf, size_t count, loff_t *index)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (*index >= bpa_nvram_len)
|
||||
return 0;
|
||||
if (*index + count > bpa_nvram_len)
|
||||
count = bpa_nvram_len - *index;
|
||||
|
||||
spin_lock_irqsave(&bpa_nvram_lock, flags);
|
||||
|
||||
memcpy_fromio(buf, bpa_nvram_start + *index, count);
|
||||
|
||||
spin_unlock_irqrestore(&bpa_nvram_lock, flags);
|
||||
|
||||
*index += count;
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t bpa_nvram_write(char *buf, size_t count, loff_t *index)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (*index >= bpa_nvram_len)
|
||||
return 0;
|
||||
if (*index + count > bpa_nvram_len)
|
||||
count = bpa_nvram_len - *index;
|
||||
|
||||
spin_lock_irqsave(&bpa_nvram_lock, flags);
|
||||
|
||||
memcpy_toio(bpa_nvram_start + *index, buf, count);
|
||||
|
||||
spin_unlock_irqrestore(&bpa_nvram_lock, flags);
|
||||
|
||||
*index += count;
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t bpa_nvram_get_size(void)
|
||||
{
|
||||
return bpa_nvram_len;
|
||||
}
|
||||
|
||||
int __init bpa_nvram_init(void)
|
||||
{
|
||||
struct device_node *nvram_node;
|
||||
unsigned long *buffer;
|
||||
int proplen;
|
||||
unsigned long nvram_addr;
|
||||
int ret;
|
||||
|
||||
ret = -ENODEV;
|
||||
nvram_node = of_find_node_by_type(NULL, "nvram");
|
||||
if (!nvram_node)
|
||||
goto out;
|
||||
|
||||
ret = -EIO;
|
||||
buffer = (unsigned long *)get_property(nvram_node, "reg", &proplen);
|
||||
if (proplen != 2*sizeof(unsigned long))
|
||||
goto out;
|
||||
|
||||
ret = -ENODEV;
|
||||
nvram_addr = buffer[0];
|
||||
bpa_nvram_len = buffer[1];
|
||||
if ( (!bpa_nvram_len) || (!nvram_addr) )
|
||||
goto out;
|
||||
|
||||
bpa_nvram_start = ioremap(nvram_addr, bpa_nvram_len);
|
||||
if (!bpa_nvram_start)
|
||||
goto out;
|
||||
|
||||
printk(KERN_INFO "BPA NVRAM, %luk mapped to %p\n",
|
||||
bpa_nvram_len >> 10, bpa_nvram_start);
|
||||
|
||||
ppc_md.nvram_read = bpa_nvram_read;
|
||||
ppc_md.nvram_write = bpa_nvram_write;
|
||||
ppc_md.nvram_size = bpa_nvram_get_size;
|
||||
|
||||
out:
|
||||
of_node_put(nvram_node);
|
||||
return ret;
|
||||
}
|
||||
@@ -0,0 +1,140 @@
|
||||
/*
|
||||
* linux/arch/ppc/kernel/bpa_setup.c
|
||||
*
|
||||
* Copyright (C) 1995 Linus Torvalds
|
||||
* Adapted from 'alpha' version by Gary Thomas
|
||||
* Modified by Cort Dougan (cort@cs.nmt.edu)
|
||||
* Modified by PPC64 Team, IBM Corp
|
||||
* Modified by BPA Team, IBM Deutschland Entwicklung GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/rtas.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/iommu.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/nvram.h>
|
||||
#include <asm/cputable.h>
|
||||
|
||||
#include "pci.h"
|
||||
#include "bpa_iic.h"
|
||||
#include "bpa_iommu.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DBG(fmt...) udbg_printf(fmt)
|
||||
#else
|
||||
#define DBG(fmt...)
|
||||
#endif
|
||||
|
||||
void bpa_get_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
struct device_node *root;
|
||||
const char *model = "";
|
||||
|
||||
root = of_find_node_by_path("/");
|
||||
if (root)
|
||||
model = get_property(root, "model", NULL);
|
||||
seq_printf(m, "machine\t\t: BPA %s\n", model);
|
||||
of_node_put(root);
|
||||
}
|
||||
|
||||
static void bpa_progress(char *s, unsigned short hex)
|
||||
{
|
||||
printk("*** %04x : %s\n", hex, s ? s : "");
|
||||
}
|
||||
|
||||
static void __init bpa_setup_arch(void)
|
||||
{
|
||||
ppc_md.init_IRQ = iic_init_IRQ;
|
||||
ppc_md.get_irq = iic_get_irq;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_init_pSeries();
|
||||
#endif
|
||||
|
||||
/* init to some ~sane value until calibrate_delay() runs */
|
||||
loops_per_jiffy = 50000000;
|
||||
|
||||
if (ROOT_DEV == 0) {
|
||||
printk("No ramdisk, default root is /dev/hda2\n");
|
||||
ROOT_DEV = Root_HDA2;
|
||||
}
|
||||
|
||||
/* Find and initialize PCI host bridges */
|
||||
init_pci_config_tokens();
|
||||
find_and_init_phbs();
|
||||
spider_init_IRQ();
|
||||
#ifdef CONFIG_DUMMY_CONSOLE
|
||||
conswitchp = &dummy_con;
|
||||
#endif
|
||||
|
||||
bpa_nvram_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* Early initialization. Relocation is on but do not reference unbolted pages
|
||||
*/
|
||||
static void __init bpa_init_early(void)
|
||||
{
|
||||
DBG(" -> bpa_init_early()\n");
|
||||
|
||||
hpte_init_native();
|
||||
|
||||
bpa_init_iommu();
|
||||
|
||||
ppc64_interrupt_controller = IC_BPA_IIC;
|
||||
|
||||
DBG(" <- bpa_init_early()\n");
|
||||
}
|
||||
|
||||
|
||||
static int __init bpa_probe(int platform)
|
||||
{
|
||||
if (platform != PLATFORM_BPA)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
struct machdep_calls __initdata bpa_md = {
|
||||
.probe = bpa_probe,
|
||||
.setup_arch = bpa_setup_arch,
|
||||
.init_early = bpa_init_early,
|
||||
.get_cpuinfo = bpa_get_cpuinfo,
|
||||
.restart = rtas_restart,
|
||||
.power_off = rtas_power_off,
|
||||
.halt = rtas_halt,
|
||||
.get_boot_time = rtas_get_boot_time,
|
||||
.get_rtc_time = rtas_get_rtc_time,
|
||||
.set_rtc_time = rtas_set_rtc_time,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = bpa_progress,
|
||||
};
|
||||
@@ -74,6 +74,20 @@ _GLOBAL(__970_cpu_preinit)
|
||||
_GLOBAL(__setup_cpu_power4)
|
||||
blr
|
||||
|
||||
_GLOBAL(__setup_cpu_be)
|
||||
/* Set large page sizes LP=0: 16MB, LP=1: 64KB */
|
||||
addi r3, 0, 0
|
||||
ori r3, r3, HID6_LB
|
||||
sldi r3, r3, 32
|
||||
nor r3, r3, r3
|
||||
mfspr r4, SPRN_HID6
|
||||
and r4, r4, r3
|
||||
addi r3, 0, 0x02000
|
||||
sldi r3, r3, 32
|
||||
or r4, r4, r3
|
||||
mtspr SPRN_HID6, r4
|
||||
blr
|
||||
|
||||
_GLOBAL(__setup_cpu_ppc970)
|
||||
mfspr r0,SPRN_HID0
|
||||
li r11,5 /* clear DOZE and SLEEP */
|
||||
|
||||
@@ -34,6 +34,7 @@ EXPORT_SYMBOL(cur_cpu_spec);
|
||||
extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
|
||||
|
||||
|
||||
/* We only set the altivec features if the kernel was compiled with altivec
|
||||
@@ -162,6 +163,16 @@ struct cpu_spec cpu_specs[] = {
|
||||
__setup_cpu_power4,
|
||||
COMMON_PPC64_FW
|
||||
},
|
||||
{ /* BE DD1.x */
|
||||
0xffff0000, 0x00700000, "Broadband Engine",
|
||||
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
|
||||
CPU_FTR_SMT,
|
||||
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
||||
128, 128,
|
||||
__setup_cpu_be,
|
||||
COMMON_PPC64_FW
|
||||
},
|
||||
{ /* default match */
|
||||
0x00000000, 0x00000000, "POWER4 (compatible)",
|
||||
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
|
||||
|
||||
@@ -671,9 +671,6 @@ static void __init iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr)
|
||||
}
|
||||
}
|
||||
|
||||
extern unsigned long ppc_proc_freq;
|
||||
extern unsigned long ppc_tb_freq;
|
||||
|
||||
/*
|
||||
* Document me.
|
||||
*/
|
||||
@@ -772,8 +769,6 @@ static void iSeries_halt(void)
|
||||
mf_power_off();
|
||||
}
|
||||
|
||||
extern void setup_default_decr(void);
|
||||
|
||||
/*
|
||||
* void __init iSeries_calibrate_decr()
|
||||
*
|
||||
|
||||
@@ -395,6 +395,9 @@ int virt_irq_create_mapping(unsigned int real_irq)
|
||||
if (ppc64_interrupt_controller == IC_OPEN_PIC)
|
||||
return real_irq; /* no mapping for openpic (for now) */
|
||||
|
||||
if (ppc64_interrupt_controller == IC_BPA_IIC)
|
||||
return real_irq; /* no mapping for iic either */
|
||||
|
||||
/* don't map interrupts < MIN_VIRT_IRQ */
|
||||
if (real_irq < MIN_VIRT_IRQ) {
|
||||
virt_irq_to_real_map[real_irq] = real_irq;
|
||||
|
||||
@@ -78,17 +78,77 @@ extern int maple_pci_get_legacy_ide_irq(struct pci_dev *dev, int channel);
|
||||
extern void generic_find_legacy_serial_ports(u64 *physport,
|
||||
unsigned int *default_speed);
|
||||
|
||||
|
||||
static void maple_restart(char *cmd)
|
||||
{
|
||||
unsigned int maple_nvram_base;
|
||||
unsigned int maple_nvram_offset;
|
||||
unsigned int maple_nvram_command;
|
||||
struct device_node *rtcs;
|
||||
|
||||
/* find NVRAM device */
|
||||
rtcs = find_compatible_devices("nvram", "AMD8111");
|
||||
if (rtcs && rtcs->addrs) {
|
||||
maple_nvram_base = rtcs->addrs[0].address;
|
||||
} else {
|
||||
printk(KERN_EMERG "Maple: Unable to find NVRAM\n");
|
||||
printk(KERN_EMERG "Maple: Manual Restart Required\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* find service processor device */
|
||||
rtcs = find_devices("service-processor");
|
||||
if (!rtcs) {
|
||||
printk(KERN_EMERG "Maple: Unable to find Service Processor\n");
|
||||
printk(KERN_EMERG "Maple: Manual Restart Required\n");
|
||||
return;
|
||||
}
|
||||
maple_nvram_offset = *(unsigned int*) get_property(rtcs,
|
||||
"restart-addr", NULL);
|
||||
maple_nvram_command = *(unsigned int*) get_property(rtcs,
|
||||
"restart-value", NULL);
|
||||
|
||||
/* send command */
|
||||
outb_p(maple_nvram_command, maple_nvram_base + maple_nvram_offset);
|
||||
for (;;) ;
|
||||
}
|
||||
|
||||
static void maple_power_off(void)
|
||||
{
|
||||
unsigned int maple_nvram_base;
|
||||
unsigned int maple_nvram_offset;
|
||||
unsigned int maple_nvram_command;
|
||||
struct device_node *rtcs;
|
||||
|
||||
/* find NVRAM device */
|
||||
rtcs = find_compatible_devices("nvram", "AMD8111");
|
||||
if (rtcs && rtcs->addrs) {
|
||||
maple_nvram_base = rtcs->addrs[0].address;
|
||||
} else {
|
||||
printk(KERN_EMERG "Maple: Unable to find NVRAM\n");
|
||||
printk(KERN_EMERG "Maple: Manual Power-Down Required\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* find service processor device */
|
||||
rtcs = find_devices("service-processor");
|
||||
if (!rtcs) {
|
||||
printk(KERN_EMERG "Maple: Unable to find Service Processor\n");
|
||||
printk(KERN_EMERG "Maple: Manual Power-Down Required\n");
|
||||
return;
|
||||
}
|
||||
maple_nvram_offset = *(unsigned int*) get_property(rtcs,
|
||||
"power-off-addr", NULL);
|
||||
maple_nvram_command = *(unsigned int*) get_property(rtcs,
|
||||
"power-off-value", NULL);
|
||||
|
||||
/* send command */
|
||||
outb_p(maple_nvram_command, maple_nvram_base + maple_nvram_offset);
|
||||
for (;;) ;
|
||||
}
|
||||
|
||||
static void maple_halt(void)
|
||||
{
|
||||
maple_power_off();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
@@ -235,6 +295,6 @@ struct machdep_calls __initdata maple_md = {
|
||||
.get_boot_time = maple_get_boot_time,
|
||||
.set_rtc_time = maple_set_rtc_time,
|
||||
.get_rtc_time = maple_get_rtc_time,
|
||||
.calibrate_decr = maple_calibrate_decr,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = maple_progress,
|
||||
};
|
||||
|
||||
@@ -42,11 +42,8 @@
|
||||
#define DBG(x...)
|
||||
#endif
|
||||
|
||||
extern void setup_default_decr(void);
|
||||
extern void GregorianDay(struct rtc_time * tm);
|
||||
|
||||
extern unsigned long ppc_tb_freq;
|
||||
extern unsigned long ppc_proc_freq;
|
||||
static int maple_rtc_addr;
|
||||
|
||||
static int maple_clock_read(int addr)
|
||||
@@ -176,51 +173,3 @@ void __init maple_get_boot_time(struct rtc_time *tm)
|
||||
maple_get_rtc_time(tm);
|
||||
}
|
||||
|
||||
/* XXX FIXME: Some sane defaults: 125 MHz timebase, 1GHz processor */
|
||||
#define DEFAULT_TB_FREQ 125000000UL
|
||||
#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
|
||||
|
||||
void __init maple_calibrate_decr(void)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
struct div_result divres;
|
||||
unsigned int *fp = NULL;
|
||||
|
||||
/*
|
||||
* The cpu node should have a timebase-frequency property
|
||||
* to tell us the rate at which the decrementer counts.
|
||||
*/
|
||||
cpu = of_find_node_by_type(NULL, "cpu");
|
||||
|
||||
ppc_tb_freq = DEFAULT_TB_FREQ;
|
||||
if (cpu != 0)
|
||||
fp = (unsigned int *)get_property(cpu, "timebase-frequency", NULL);
|
||||
if (fp != NULL)
|
||||
ppc_tb_freq = *fp;
|
||||
else
|
||||
printk(KERN_ERR "WARNING: Estimating decrementer frequency (not found)\n");
|
||||
fp = NULL;
|
||||
ppc_proc_freq = DEFAULT_PROC_FREQ;
|
||||
if (cpu != 0)
|
||||
fp = (unsigned int *)get_property(cpu, "clock-frequency", NULL);
|
||||
if (fp != NULL)
|
||||
ppc_proc_freq = *fp;
|
||||
else
|
||||
printk(KERN_ERR "WARNING: Estimating processor frequency (not found)\n");
|
||||
|
||||
of_node_put(cpu);
|
||||
|
||||
printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
|
||||
ppc_tb_freq/1000000, ppc_tb_freq%1000000);
|
||||
printk(KERN_INFO "time_init: processor frequency = %lu.%.6lu MHz\n",
|
||||
ppc_proc_freq/1000000, ppc_proc_freq%1000000);
|
||||
|
||||
tb_ticks_per_jiffy = ppc_tb_freq / HZ;
|
||||
tb_ticks_per_sec = tb_ticks_per_jiffy * HZ;
|
||||
tb_ticks_per_usec = ppc_tb_freq / 1000000;
|
||||
tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
|
||||
div128_by_32(1024*1024, 0, tb_ticks_per_sec, &divres);
|
||||
tb_to_xs = divres.result_low;
|
||||
|
||||
setup_default_decr();
|
||||
}
|
||||
|
||||
@@ -265,3 +265,6 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
|
||||
extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
|
||||
/* This one gets to the primary mpic */
|
||||
extern int mpic_get_irq(struct pt_regs *regs);
|
||||
|
||||
/* global mpic for pSeries */
|
||||
extern struct mpic *pSeries_mpic;
|
||||
|
||||
+18
-477
File diff suppressed because it is too large
Load Diff
@@ -71,11 +71,6 @@
|
||||
#define DBG(fmt...)
|
||||
#endif
|
||||
|
||||
extern void pSeries_final_fixup(void);
|
||||
|
||||
extern void pSeries_get_boot_time(struct rtc_time *rtc_time);
|
||||
extern void pSeries_get_rtc_time(struct rtc_time *rtc_time);
|
||||
extern int pSeries_set_rtc_time(struct rtc_time *rtc_time);
|
||||
extern void find_udbg_vterm(void);
|
||||
extern void system_reset_fwnmi(void); /* from head.S */
|
||||
extern void machine_check_fwnmi(void); /* from head.S */
|
||||
@@ -84,9 +79,6 @@ extern void generic_find_legacy_serial_ports(u64 *physport,
|
||||
|
||||
int fwnmi_active; /* TRUE if an FWNMI handler is present */
|
||||
|
||||
extern unsigned long ppc_proc_freq;
|
||||
extern unsigned long ppc_tb_freq;
|
||||
|
||||
extern void pSeries_system_reset_exception(struct pt_regs *regs);
|
||||
extern int pSeries_machine_check_exception(struct pt_regs *regs);
|
||||
|
||||
@@ -381,171 +373,6 @@ static void __init pSeries_init_early(void)
|
||||
}
|
||||
|
||||
|
||||
static void pSeries_progress(char *s, unsigned short hex)
|
||||
{
|
||||
struct device_node *root;
|
||||
int width, *p;
|
||||
char *os;
|
||||
static int display_character, set_indicator;
|
||||
static int max_width;
|
||||
static DEFINE_SPINLOCK(progress_lock);
|
||||
static int pending_newline = 0; /* did last write end with unprinted newline? */
|
||||
|
||||
if (!rtas.base)
|
||||
return;
|
||||
|
||||
if (max_width == 0) {
|
||||
if ((root = find_path_device("/rtas")) &&
|
||||
(p = (unsigned int *)get_property(root,
|
||||
"ibm,display-line-length",
|
||||
NULL)))
|
||||
max_width = *p;
|
||||
else
|
||||
max_width = 0x10;
|
||||
display_character = rtas_token("display-character");
|
||||
set_indicator = rtas_token("set-indicator");
|
||||
}
|
||||
|
||||
if (display_character == RTAS_UNKNOWN_SERVICE) {
|
||||
/* use hex display if available */
|
||||
if (set_indicator != RTAS_UNKNOWN_SERVICE)
|
||||
rtas_call(set_indicator, 3, 1, NULL, 6, 0, hex);
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock(&progress_lock);
|
||||
|
||||
/*
|
||||
* Last write ended with newline, but we didn't print it since
|
||||
* it would just clear the bottom line of output. Print it now
|
||||
* instead.
|
||||
*
|
||||
* If no newline is pending, print a CR to start output at the
|
||||
* beginning of the line.
|
||||
*/
|
||||
if (pending_newline) {
|
||||
rtas_call(display_character, 1, 1, NULL, '\r');
|
||||
rtas_call(display_character, 1, 1, NULL, '\n');
|
||||
pending_newline = 0;
|
||||
} else {
|
||||
rtas_call(display_character, 1, 1, NULL, '\r');
|
||||
}
|
||||
|
||||
width = max_width;
|
||||
os = s;
|
||||
while (*os) {
|
||||
if (*os == '\n' || *os == '\r') {
|
||||
/* Blank to end of line. */
|
||||
while (width-- > 0)
|
||||
rtas_call(display_character, 1, 1, NULL, ' ');
|
||||
|
||||
/* If newline is the last character, save it
|
||||
* until next call to avoid bumping up the
|
||||
* display output.
|
||||
*/
|
||||
if (*os == '\n' && !os[1]) {
|
||||
pending_newline = 1;
|
||||
spin_unlock(&progress_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
/* RTAS wants CR-LF, not just LF */
|
||||
|
||||
if (*os == '\n') {
|
||||
rtas_call(display_character, 1, 1, NULL, '\r');
|
||||
rtas_call(display_character, 1, 1, NULL, '\n');
|
||||
} else {
|
||||
/* CR might be used to re-draw a line, so we'll
|
||||
* leave it alone and not add LF.
|
||||
*/
|
||||
rtas_call(display_character, 1, 1, NULL, *os);
|
||||
}
|
||||
|
||||
width = max_width;
|
||||
} else {
|
||||
width--;
|
||||
rtas_call(display_character, 1, 1, NULL, *os);
|
||||
}
|
||||
|
||||
os++;
|
||||
|
||||
/* if we overwrite the screen length */
|
||||
if (width <= 0)
|
||||
while ((*os != 0) && (*os != '\n') && (*os != '\r'))
|
||||
os++;
|
||||
}
|
||||
|
||||
/* Blank to end of line. */
|
||||
while (width-- > 0)
|
||||
rtas_call(display_character, 1, 1, NULL, ' ');
|
||||
|
||||
spin_unlock(&progress_lock);
|
||||
}
|
||||
|
||||
extern void setup_default_decr(void);
|
||||
|
||||
/* Some sane defaults: 125 MHz timebase, 1GHz processor */
|
||||
#define DEFAULT_TB_FREQ 125000000UL
|
||||
#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
|
||||
|
||||
static void __init pSeries_calibrate_decr(void)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
struct div_result divres;
|
||||
unsigned int *fp;
|
||||
int node_found;
|
||||
|
||||
/*
|
||||
* The cpu node should have a timebase-frequency property
|
||||
* to tell us the rate at which the decrementer counts.
|
||||
*/
|
||||
cpu = of_find_node_by_type(NULL, "cpu");
|
||||
|
||||
ppc_tb_freq = DEFAULT_TB_FREQ; /* hardcoded default */
|
||||
node_found = 0;
|
||||
if (cpu != 0) {
|
||||
fp = (unsigned int *)get_property(cpu, "timebase-frequency",
|
||||
NULL);
|
||||
if (fp != 0) {
|
||||
node_found = 1;
|
||||
ppc_tb_freq = *fp;
|
||||
}
|
||||
}
|
||||
if (!node_found)
|
||||
printk(KERN_ERR "WARNING: Estimating decrementer frequency "
|
||||
"(not found)\n");
|
||||
|
||||
ppc_proc_freq = DEFAULT_PROC_FREQ;
|
||||
node_found = 0;
|
||||
if (cpu != 0) {
|
||||
fp = (unsigned int *)get_property(cpu, "clock-frequency",
|
||||
NULL);
|
||||
if (fp != 0) {
|
||||
node_found = 1;
|
||||
ppc_proc_freq = *fp;
|
||||
}
|
||||
}
|
||||
if (!node_found)
|
||||
printk(KERN_ERR "WARNING: Estimating processor frequency "
|
||||
"(not found)\n");
|
||||
|
||||
of_node_put(cpu);
|
||||
|
||||
printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
|
||||
ppc_tb_freq/1000000, ppc_tb_freq%1000000);
|
||||
printk(KERN_INFO "time_init: processor frequency = %lu.%.6lu MHz\n",
|
||||
ppc_proc_freq/1000000, ppc_proc_freq%1000000);
|
||||
|
||||
tb_ticks_per_jiffy = ppc_tb_freq / HZ;
|
||||
tb_ticks_per_sec = tb_ticks_per_jiffy * HZ;
|
||||
tb_ticks_per_usec = ppc_tb_freq / 1000000;
|
||||
tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
|
||||
div128_by_32(1024*1024, 0, tb_ticks_per_sec, &divres);
|
||||
tb_to_xs = divres.result_low;
|
||||
|
||||
setup_default_decr();
|
||||
}
|
||||
|
||||
static int pSeries_check_legacy_ioport(unsigned int baseport)
|
||||
{
|
||||
struct device_node *np;
|
||||
@@ -596,16 +423,17 @@ struct machdep_calls __initdata pSeries_md = {
|
||||
.get_cpuinfo = pSeries_get_cpuinfo,
|
||||
.log_error = pSeries_log_error,
|
||||
.pcibios_fixup = pSeries_final_fixup,
|
||||
.irq_bus_setup = pSeries_irq_bus_setup,
|
||||
.restart = rtas_restart,
|
||||
.power_off = rtas_power_off,
|
||||
.halt = rtas_halt,
|
||||
.panic = rtas_os_term,
|
||||
.cpu_die = pSeries_mach_cpu_die,
|
||||
.get_boot_time = pSeries_get_boot_time,
|
||||
.get_rtc_time = pSeries_get_rtc_time,
|
||||
.set_rtc_time = pSeries_set_rtc_time,
|
||||
.calibrate_decr = pSeries_calibrate_decr,
|
||||
.progress = pSeries_progress,
|
||||
.get_boot_time = rtas_get_boot_time,
|
||||
.get_rtc_time = rtas_get_rtc_time,
|
||||
.set_rtc_time = rtas_set_rtc_time,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = rtas_progress,
|
||||
.check_legacy_ioport = pSeries_check_legacy_ioport,
|
||||
.system_reset_exception = pSeries_system_reset_exception,
|
||||
.machine_check_exception = pSeries_machine_check_exception,
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SMP support for pSeries machines.
|
||||
* SMP support for pSeries and BPA machines.
|
||||
*
|
||||
* Dave Engebretsen, Peter Bergner, and
|
||||
* Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
|
||||
@@ -47,6 +47,7 @@
|
||||
#include <asm/pSeries_reconfig.h>
|
||||
|
||||
#include "mpic.h"
|
||||
#include "bpa_iic.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DBG(fmt...) udbg_printf(fmt)
|
||||
@@ -286,6 +287,7 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu)
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_XICS
|
||||
static inline void smp_xics_do_message(int cpu, int msg)
|
||||
{
|
||||
set_bit(msg, &xics_ipi_message[cpu].value);
|
||||
@@ -327,6 +329,37 @@ static void __devinit smp_xics_setup_cpu(int cpu)
|
||||
cpu_clear(cpu, of_spin_map);
|
||||
|
||||
}
|
||||
#endif /* CONFIG_XICS */
|
||||
#ifdef CONFIG_BPA_IIC
|
||||
static void smp_iic_message_pass(int target, int msg)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (target < NR_CPUS) {
|
||||
iic_cause_IPI(target, msg);
|
||||
} else {
|
||||
for_each_online_cpu(i) {
|
||||
if (target == MSG_ALL_BUT_SELF
|
||||
&& i == smp_processor_id())
|
||||
continue;
|
||||
iic_cause_IPI(i, msg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int __init smp_iic_probe(void)
|
||||
{
|
||||
iic_request_IPIs();
|
||||
|
||||
return cpus_weight(cpu_possible_map);
|
||||
}
|
||||
|
||||
static void __devinit smp_iic_setup_cpu(int cpu)
|
||||
{
|
||||
if (cpu != boot_cpuid)
|
||||
iic_setup_cpu();
|
||||
}
|
||||
#endif /* CONFIG_BPA_IIC */
|
||||
|
||||
static DEFINE_SPINLOCK(timebase_lock);
|
||||
static unsigned long timebase = 0;
|
||||
@@ -381,14 +414,15 @@ static int smp_pSeries_cpu_bootable(unsigned int nr)
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MPIC
|
||||
static struct smp_ops_t pSeries_mpic_smp_ops = {
|
||||
.message_pass = smp_mpic_message_pass,
|
||||
.probe = smp_mpic_probe,
|
||||
.kick_cpu = smp_pSeries_kick_cpu,
|
||||
.setup_cpu = smp_mpic_setup_cpu,
|
||||
};
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_XICS
|
||||
static struct smp_ops_t pSeries_xics_smp_ops = {
|
||||
.message_pass = smp_xics_message_pass,
|
||||
.probe = smp_xics_probe,
|
||||
@@ -396,6 +430,16 @@ static struct smp_ops_t pSeries_xics_smp_ops = {
|
||||
.setup_cpu = smp_xics_setup_cpu,
|
||||
.cpu_bootable = smp_pSeries_cpu_bootable,
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_BPA_IIC
|
||||
static struct smp_ops_t bpa_iic_smp_ops = {
|
||||
.message_pass = smp_iic_message_pass,
|
||||
.probe = smp_iic_probe,
|
||||
.kick_cpu = smp_pSeries_kick_cpu,
|
||||
.setup_cpu = smp_iic_setup_cpu,
|
||||
.cpu_bootable = smp_pSeries_cpu_bootable,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* This is called very early */
|
||||
void __init smp_init_pSeries(void)
|
||||
@@ -404,10 +448,25 @@ void __init smp_init_pSeries(void)
|
||||
|
||||
DBG(" -> smp_init_pSeries()\n");
|
||||
|
||||
if (ppc64_interrupt_controller == IC_OPEN_PIC)
|
||||
switch (ppc64_interrupt_controller) {
|
||||
#ifdef CONFIG_MPIC
|
||||
case IC_OPEN_PIC:
|
||||
smp_ops = &pSeries_mpic_smp_ops;
|
||||
else
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_XICS
|
||||
case IC_PPC_XIC:
|
||||
smp_ops = &pSeries_xics_smp_ops;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_BPA_IIC
|
||||
case IC_BPA_IIC:
|
||||
smp_ops = &bpa_iic_smp_ops;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
panic("Invalid interrupt controller");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
smp_ops->cpu_disable = pSeries_cpu_disable;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user