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Linux-2.6.12-rc2

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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
This commit is contained in:
Linus Torvalds
2005-04-16 15:20:36 -07:00
commit 1da177e4c3
17291 changed files with 6718755 additions and 0 deletions
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include/asm-mips/sn/addrs.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 1999, 2000 by Ralf Baechle
*/
#ifndef _ASM_SN_ADDRS_H
#define _ASM_SN_ADDRS_H
#include <linux/config.h>
#ifndef __ASSEMBLY__
#include <linux/types.h>
#endif /* !__ASSEMBLY__ */
#include <asm/addrspace.h>
#include <asm/sn/kldir.h>
#if defined(CONFIG_SGI_IP27)
#include <asm/sn/sn0/addrs.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/addrs.h>
#endif
#ifndef __ASSEMBLY__
#if defined(CONFIG_SGI_IO) /* FIXME */
#define PS_UINT_CAST (__psunsigned_t)
#define UINT64_CAST (__uint64_t)
#else /* CONFIG_SGI_IO */
#define PS_UINT_CAST (unsigned long)
#define UINT64_CAST (unsigned long)
#endif /* CONFIG_SGI_IO */
#define HUBREG_CAST (volatile hubreg_t *)
#else /* __ASSEMBLY__ */
#define PS_UINT_CAST
#define UINT64_CAST
#define HUBREG_CAST
#endif /* __ASSEMBLY__ */
#define NASID_GET_META(_n) ((_n) >> NASID_LOCAL_BITS)
#ifdef CONFIG_SGI_IP27
#define NASID_GET_LOCAL(_n) ((_n) & 0xf)
#endif
#define NASID_MAKE(_m, _l) (((_m) << NASID_LOCAL_BITS) | (_l))
#define NODE_ADDRSPACE_MASK (NODE_ADDRSPACE_SIZE - 1)
#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
#define CHANGE_ADDR_NASID(_pa, _nasid) \
((UINT64_CAST (_pa) & ~NASID_MASK) | \
(UINT64_CAST(_nasid) << NASID_SHFT))
/*
* The following macros are used to index to the beginning of a specific
* node's address space.
*/
#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS)
#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n))
#define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n))
#define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n))
#define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n))
#define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n))
#define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) ))
#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
#define RAW_NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
/*
* The following definitions pertain to the IO special address
* space. They define the location of the big and little windows
* of any given node.
*/
#define SWIN_SIZE_BITS 24
#define SWIN_SIZE (UINT64_CAST 1 << 24)
#define SWIN_SIZEMASK (SWIN_SIZE - 1)
#define SWIN_WIDGET_MASK 0xF
/*
* Convert smallwindow address to xtalk address.
*
* 'addr' can be physical or virtual address, but will be converted
* to Xtalk address in the range 0 -> SWINZ_SIZEMASK
*/
#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK)
#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
/*
* Verify if addr belongs to small window address on node with "nasid"
*
*
* NOTE: "addr" is expected to be XKPHYS address, and NOT physical
* address
*
*
*/
#define NODE_SWIN_ADDR(nasid, addr) \
(((addr) >= NODE_SWIN_BASE(nasid, 0)) && \
((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
))
/*
* The following define the major position-independent aliases used
* in SN.
* UALIAS -- 256MB in size, reads in the UALIAS result in
* uncached references to the memory of the reader's node.
* CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
* depending on which CPU does the access to provide
* all CPUs with unique uncached memory at low addresses.
* LBOOT -- 256MB in size, reads in the LBOOT area result in
* uncached references to the local hub's boot prom and
* other directory-bus connected devices.
* IALIAS -- 8MB in size, reads in the IALIAS result in uncached
* references to the local hub's registers.
*/
#define UALIAS_BASE HSPEC_BASE
#define UALIAS_SIZE 0x10000000 /* 256 Megabytes */
#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE)
/*
* The bottom of ualias space is flipped depending on whether you're
* processor 0 or 1 within a node.
*/
#ifdef CONFIG_SGI_IP27
#define UALIAS_FLIP_BASE UALIAS_BASE
#define UALIAS_FLIP_SIZE 0x20000
#define UALIAS_FLIP_BIT 0x10000
#define UALIAS_FLIP_ADDR(_x) (cputoslice(smp_processor_id()) ? \
(_x) ^ UALIAS_FLIP_BIT : (_x))
#define LBOOT_BASE (HSPEC_BASE + 0x10000000)
#define LBOOT_SIZE 0x10000000
#define LBOOT_LIMIT (LBOOT_BASE + LBOOT_SIZE)
#define LBOOT_STRIDE 0 /* IP27 has only one CPU PROM */
#endif
#define HUB_REGISTER_WIDGET 1
#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
#define IALIAS_SIZE 0x800000 /* 8 Megabytes */
#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \
((_a) < (IALIAS_BASE + IALIAS_SIZE)))
/*
* Macro for referring to Hub's RBOOT space
*/
#ifdef CONFIG_SGI_IP27
#define RBOOT_SIZE 0x10000000 /* 256 Megabytes */
#define NODE_RBOOT_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000)
#define NODE_RBOOT_LIMIT(_n) (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
#endif
/*
* Macros for referring the Hub's back door space
*
* These macros correctly process addresses in any node's space.
* WARNING: They won't work in assembler.
*
* BDDIR_ENTRY_LO returns the address of the low double-word of the dir
* entry corresponding to a physical (Cac or Uncac) address.
* BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
* BDPRT_ENTRY returns the address of the double-word protection entry
* corresponding to the page containing the physical address.
* BDPRT_ENTRY_S Stores the value into the protection entry.
* BDPRT_ENTRY_L Load the value from the protection entry.
* BDECC_ENTRY returns the address of the ECC byte corresponding to a
* double-word at a specified physical address.
* BDECC_ENTRY_H returns the address of the two ECC bytes corresponding to a
* quad-word at a specified physical address.
*/
#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
#define NODE_BDECC_BASE(_n) (NODE_BDOOR_BASE(_n))
#define NODE_BDDIR_BASE(_n) (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
#ifdef CONFIG_SGI_IP27
#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE * 3 / 4 + \
0x200) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST (_pa) >> 3 & 0x1f << 4)
#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE * 3 / 4 + \
0x208) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST (_pa) >> 3 & 0x1f << 4)
#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE * 3 / 4) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
(_rgn) << 3)
#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn)))
#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val))
#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn)))
#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
NODE_ADDRSPACE_SIZE / 2) | \
UINT64_CAST (_pa) & NASID_MASK | \
UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \
UINT64_CAST (_pa) >> 3 & 3)
/*
* Macro to convert a back door directory or protection address into the
* raw physical address of the associated cache line or protection page.
*/
#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \
(UINT64_CAST (_ba) & 0x1f << 4) << 3)
#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2)
#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \
(UINT64_CAST (_ba) & 3) << 3)
#endif /* CONFIG_SGI_IP27 */
/*
* The following macros produce the correct base virtual address for
* the hub registers. The LOCAL_HUB_* macros produce the appropriate
* address for the local registers. The REMOTE_HUB_* macro produce
* the address for the specified hub's registers. The intent is
* that the appropriate PI, MD, NI, or II register would be substituted
* for _x.
*/
#ifdef _STANDALONE
/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#endif /* _STANDALONE */
/*
* WARNING:
* When certain Hub chip workaround are defined, it's not sufficient
* to dereference the *_HUB_ADDR() macros. You should instead use
* HUB_L() and HUB_S() if you must deal with pointers to hub registers.
* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
* They're always safe.
*/
#define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#ifdef CONFIG_SGI_IP27
#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#endif /* CONFIG_SGI_IP27 */
#ifndef __ASSEMBLY__
#define HUB_L(_a) *(_a)
#define HUB_S(_a, _d) *(_a) = (_d)
#define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r))
#define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d))
#define REMOTE_HUB_L(_n, _r) HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
#define REMOTE_HUB_S(_n, _r, _d) HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
#define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
#endif /* !__ASSEMBLY__ */
/*
* The following macros are used to get to a hub/bridge register, given
* the base of the register space.
*/
#define HUB_REG_PTR(_base, _off) \
(HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
#define HUB_REG_PTR_L(_base, _off) \
HUB_L(HUB_REG_PTR((_base), (_off)))
#define HUB_REG_PTR_S(_base, _off, _data) \
HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
/*
* Software structure locations -- permanently fixed
* See diagram in kldir.h
*/
#define PHYS_RAMBASE 0x0
#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE)
#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
#define EX_HANDLER_ADDR(nasid, slice) \
PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
#define EX_HANDLER_SIZE 0x0400
#define EX_FRAME_OFFSET(slice) ((slice) << 16 | 0x400)
#define EX_FRAME_ADDR(nasid, slice) \
PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
#define EX_FRAME_SIZE 0x0c00
#define ARCS_SPB_OFFSET 0x1000
#define ARCS_SPB_ADDR(nasid) \
PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
#define ARCS_SPB_SIZE 0x0400
#ifdef _STANDALONE
#define ARCS_TVECTOR_OFFSET 0x2800
#define ARCS_PVECTOR_OFFSET 0x2c00
/*
* These addresses are used by the master CPU to install the transfer
* and private vectors. All others use the SPB to find them.
*/
#define TVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
#define PVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
#endif /* _STANDALONE */
#define KLDIR_OFFSET 0x2000
#define KLDIR_ADDR(nasid) \
TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
#define KLDIR_SIZE 0x0400
/*
* Software structure locations -- indirected through KLDIR
* See diagram in kldir.h
*
* Important: All low memory structures must only be accessed
* uncached, except for the symmon stacks.
*/
#define KLI_LAUNCH 0 /* Dir. entries */
#define KLI_KLCONFIG 1
#define KLI_NMI 2
#define KLI_GDA 3
#define KLI_FREEMEM 4
#define KLI_SYMMON_STK 5
#define KLI_PI_ERROR 6
#define KLI_KERN_VARS 7
#define KLI_KERN_XP 8
#define KLI_KERN_PARTID 9
#ifndef __ASSEMBLY__
#define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid))
#define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH)
#define KLD_NMI(nasid) (KLD_BASE(nasid) + KLI_NMI)
#define KLD_KLCONFIG(nasid) (KLD_BASE(nasid) + KLI_KLCONFIG)
#define KLD_PI_ERROR(nasid) (KLD_BASE(nasid) + KLI_PI_ERROR)
#define KLD_GDA(nasid) (KLD_BASE(nasid) + KLI_GDA)
#define KLD_SYMMON_STK(nasid) (KLD_BASE(nasid) + KLI_SYMMON_STK)
#define KLD_FREEMEM(nasid) (KLD_BASE(nasid) + KLI_FREEMEM)
#define KLD_KERN_VARS(nasid) (KLD_BASE(nasid) + KLI_KERN_VARS)
#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP)
#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID)
#define LAUNCH_OFFSET(nasid, slice) \
(KLD_LAUNCH(nasid)->offset + \
KLD_LAUNCH(nasid)->stride * (slice))
#define LAUNCH_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size
#define NMI_OFFSET(nasid, slice) \
(KLD_NMI(nasid)->offset + \
KLD_NMI(nasid)->stride * (slice))
#define NMI_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
#define KLCONFIG_ADDR(nasid) \
TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
#define KLCONFIG_SIZE(nasid) KLD_KLCONFIG(nasid)->size
#define GDA_ADDR(nasid) KLD_GDA(nasid)->pointer
#define GDA_SIZE(nasid) KLD_GDA(nasid)->size
#define SYMMON_STK_OFFSET(nasid, slice) \
(KLD_SYMMON_STK(nasid)->offset + \
KLD_SYMMON_STK(nasid)->stride * (slice))
#define SYMMON_STK_STRIDE(nasid) KLD_SYMMON_STK(nasid)->stride
#define SYMMON_STK_ADDR(nasid, slice) \
TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
#define SYMMON_STK_SIZE(nasid) KLD_SYMMON_STK(nasid)->stride
#define SYMMON_STK_END(nasid) (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
* relocatable program
*/
#define UNIX_DEBUG_LOADADDR 0x300000
#define SYMMON_LOADADDR(nasid) \
TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
#define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset
#define FREEMEM_ADDR(nasid) SYMMON_STK_END(nasid)
/*
* XXX
* Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
* Also, it should take into account what prom thinks to be a safe
* address
PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
*/
#define FREEMEM_SIZE(nasid) KLD_FREEMEM(nasid)->size
#define PI_ERROR_OFFSET(nasid) KLD_PI_ERROR(nasid)->offset
#define PI_ERROR_ADDR(nasid) \
TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
#define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size
#define NODE_OFFSET_TO_K0(_nasid, _off) \
PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
#define NODE_OFFSET_TO_K1(_nasid, _off) \
TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
#define K0_TO_NODE_OFFSET(_k0addr) \
((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer
#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size
#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer
#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size
#define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_SN_ADDRS_H */
include/asm-mips/sn/agent.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This file has definitions for the hub and snac interfaces.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SGI_SN_AGENT_H
#define _ASM_SGI_SN_AGENT_H
#include <linux/config.h>
#include <linux/topology.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#if defined(CONFIG_SGI_IP27)
#include <asm/sn/sn0/hub.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/hub.h>
#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
/*
* NIC register macros
*/
#if defined(CONFIG_SGI_IP27)
#define HUB_NIC_ADDR(_cpuid) \
REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \
MD_MLAN_CTL)
#endif
#define SET_HUB_NIC(_my_cpuid, _val) \
(HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
#define SET_MY_HUB_NIC(_v) \
SET_HUB_NIC(cpuid(), (_v))
#define GET_HUB_NIC(_my_cpuid) \
(HUB_L(HUB_NIC_ADDR(_my_cpuid)))
#define GET_MY_HUB_NIC() \
GET_HUB_NIC(cpuid())
#endif /* _ASM_SGI_SN_AGENT_H */
include/asm-mips/sn/arch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI specific setup.
*
* Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SN_ARCH_H
#define _ASM_SN_ARCH_H
#include <linux/config.h>
#include <linux/types.h>
#include <asm/sn/types.h>
#ifdef CONFIG_SGI_IP27
#include <asm/sn/sn0/arch.h>
#endif
typedef u64 hubreg_t;
typedef u64 nic_t;
#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid)
#define cputoslice(cpu) (cpu_data[(cpu)].p_slice)
#define makespnum(_nasid, _slice) \
(((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
#define INVALID_NASID (nasid_t)-1
#define INVALID_CNODEID (cnodeid_t)-1
#define INVALID_PNODEID (pnodeid_t)-1
#define INVALID_MODULE (moduleid_t)-1
#define INVALID_PARTID (partid_t)-1
extern nasid_t get_nasid(void);
extern cnodeid_t get_cpu_cnode(cpuid_t);
extern int get_cpu_slice(cpuid_t);
/*
* NO ONE should access these arrays directly. The only reason we refer to
* them here is to avoid the procedure call that would be required in the
* macros below. (Really want private data members here :-)
*/
extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
/*
* These macros are used by various parts of the kernel to convert
* between the three different kinds of node numbering. At least some
* of them may change to procedure calls in the future, but the macros
* will continue to work. Don't use the arrays above directly.
*/
#define NASID_TO_REGION(nnode) \
((nnode) >> \
(is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
#define NASID_TO_COMPACT_NODEID(nnode) (nasid_to_compact_node[nnode])
#define COMPACT_TO_NASID_NODEID(cnode) (compact_to_nasid_node[cnode])
#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)])
#endif /* _ASM_SN_ARCH_H */
include/asm-mips/sn/gda.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/gda.h>.
*
* Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
*
* gda.h -- Contains the data structure for the global data area,
* The GDA contains information communicated between the
* PROM, SYMMON, and the kernel.
*/
#ifndef _ASM_SN_GDA_H
#define _ASM_SN_GDA_H
#include <asm/sn/addrs.h>
#define GDA_MAGIC 0x58464552
/*
* GDA Version History
*
* Version # | Change
* -------------+-------------------------------------------------------
* 1 | Initial SN0 version
* 2 | Prom sets g_partid field to the partition number. 0 IS
* | a valid partition #.
*/
#define GDA_VERSION 2 /* Current GDA version # */
#define G_MAGICOFF 0
#define G_VERSIONOFF 4
#define G_PROMOPOFF 6
#define G_MASTEROFF 8
#define G_VDSOFF 12
#define G_HKDNORMOFF 16
#define G_HKDUTLBOFF 24
#define G_HKDXUTLBOFF 32
#define G_PARTIDOFF 40
#define G_TABLEOFF 128
#ifndef __ASSEMBLY__
typedef struct gda {
u32 g_magic; /* GDA magic number */
u16 g_version; /* Version of this structure */
u16 g_masterid; /* The NASID:CPUNUM of the master cpu */
u32 g_promop; /* Passes requests from the kernel to prom */
u32 g_vds; /* Store the virtual dipswitches here */
void **g_hooked_norm;/* ptr to pda loc for norm hndlr */
void **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
void **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
int g_partid; /* partition id */
int g_symmax; /* Max symbols in name table. */
void *g_dbstab; /* Address of idbg symbol table */
char *g_nametab; /* Address of idbg name table */
void *g_ktext_repmask;
/* Pointer to a mask of nodes with copies
* of the kernel. */
char g_padding[56]; /* pad out to 128 bytes */
nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
* indexed by cnodeid.
*/
} gda_t;
#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
#endif /* !__ASSEMBLY__ */
/*
* Define: PART_GDA_VERSION
* Purpose: Define the minimum version of the GDA required, lower
* revisions assume GDA is NOT set up, and read partition
* information from the board info.
*/
#define PART_GDA_VERSION 2
/*
* The following requests can be sent to the PROM during startup.
*/
#define PROMOP_MAGIC 0x0ead0000
#define PROMOP_MAGIC_MASK 0x0fff0000
#define PROMOP_BIST_SHIFT 11
#define PROMOP_BIST_MASK (0x3 << 11)
#define PROMOP_REG PI_ERR_STACK_ADDR_A
#define PROMOP_INVALID (PROMOP_MAGIC | 0x00)
#define PROMOP_HALT (PROMOP_MAGIC | 0x10)
#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20)
#define PROMOP_RESTART (PROMOP_MAGIC | 0x30)
#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40)
#define PROMOP_IMODE (PROMOP_MAGIC | 0x50)
#define PROMOP_CMD_MASK 0x00f0
#define PROMOP_OPTIONS_MASK 0xfff0
#define PROMOP_SKIP_DIAGS 0x0100 /* don't bother running diags */
#define PROMOP_SKIP_MEMINIT 0x0200 /* don't bother initing memory */
#define PROMOP_SKIP_DEVINIT 0x0400 /* don't bother initing devices */
#define PROMOP_BIST1 0x0800 /* keep track of which BIST ran */
#define PROMOP_BIST2 0x1000 /* keep track of which BIST ran */
#endif /* _ASM_SN_GDA_H */
include/asm-mips/sn/hub.h
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#ifndef __ASM_SN_HUB_H
#define __ASM_SN_HUB_H
#include <linux/types.h>
#include <linux/cpumask.h>
#include <asm/sn/types.h>
#include <asm/sn/io.h>
#include <asm/sn/klkernvars.h>
#include <asm/xtalk/xtalk.h>
/* ip27-hubio.c */
extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
unsigned long xtalk_addr, size_t size);
extern void hub_pio_init(cnodeid_t cnode);
#endif /* __ASM_SN_HUB_H */
include/asm-mips/sn/intr.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_INTR_H
#define __ASM_SN_INTR_H
/* Number of interrupt levels associated with each interrupt register. */
#define N_INTPEND_BITS 64
#define INT_PEND0_BASELVL 0
#define INT_PEND1_BASELVL 64
#define N_INTPENDJUNK_BITS 8
#define INTPENDJUNK_CLRBIT 0x80
/*
* Macros to manipulate the interrupt register on the calling hub chip.
*/
#define LOCAL_HUB_SEND_INTR(level) \
LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
#define REMOTE_HUB_SEND_INTR(hub, level) \
REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
/*
* When clearing the interrupt, make sure this clear does make it
* to the hub. Otherwise we could end up losing interrupts.
* We do an uncached load of the int_pend0 register to ensure this.
*/
#define LOCAL_HUB_CLR_INTR(level) \
do { \
LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \
LOCAL_HUB_L(PI_INT_PEND0); \
} while (0);
#define REMOTE_HUB_CLR_INTR(hub, level) \
do { \
nasid_t __hub = (hub); \
\
REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \
REMOTE_HUB_L(__hub, PI_INT_PEND0); \
} while (0);
/*
* Hard-coded interrupt levels:
*/
/*
* L0 = SW1
* L1 = SW2
* L2 = INT_PEND0
* L3 = INT_PEND1
* L4 = RTC
* L5 = Profiling Timer
* L6 = Hub Errors
* L7 = Count/Compare (T5 counters)
*/
/*
* INT_PEND0 hard-coded bits.
*/
/*
* INT_PEND0 bits determined by hardware:
*/
#define RESERVED_INTR 0 /* What is this bit? */
#define GFX_INTR_A 1
#define GFX_INTR_B 2
#define PG_MIG_INTR 3
#define UART_INTR 4
#define CC_PEND_A 5
#define CC_PEND_B 6
/*
* INT_PEND0 used by the kernel for itself ...
*/
#define CPU_RESCHED_A_IRQ 7
#define CPU_RESCHED_B_IRQ 8
#define CPU_CALL_A_IRQ 9
#define CPU_CALL_B_IRQ 10
#define MSC_MESG_INTR 11
#define BASE_PCI_IRQ 12
/*
* INT_PEND0 again, bits determined by hardware / hardcoded:
*/
#define SDISK_INTR 63 /* SABLE name */
#define IP_PEND0_6_63 63 /* What is this bit? */
/*
* INT_PEND1 hard-coded bits:
*/
#define NI_BRDCAST_ERR_A 39
#define NI_BRDCAST_ERR_B 40
#define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */
#define LLP_PFAIL_INTR_B 42
#define TLB_INTR_A 43 /* used for tlb flush random */
#define TLB_INTR_B 44
#define IP27_INTR_0 45 /* Reserved for PROM use */
#define IP27_INTR_1 46 /* do not use in Kernel */
#define IP27_INTR_2 47
#define IP27_INTR_3 48
#define IP27_INTR_4 49
#define IP27_INTR_5 50
#define IP27_INTR_6 51
#define IP27_INTR_7 52
#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */
/* Bridge Errors */
#define DEBUG_INTR_A 54
#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */
#define IO_ERROR_INTR 57 /* Setup by PROM */
#define CLK_ERR_INTR 58
#define COR_ERR_INTR_A 59
#define COR_ERR_INTR_B 60
#define MD_COR_ERR_INTR 61
#define NI_ERROR_INTR 62
#define MSC_PANIC_INTR 63
#endif /* __ASM_SN_INTR_H */
include/asm-mips/sn/io.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000, 2003 Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_SN_IO_H
#define _ASM_SN_IO_H
#include <linux/config.h>
#if defined (CONFIG_SGI_IP27)
#include <asm/sn/sn0/hubio.h>
#endif
#define IIO_ITTE_BASE 0x400160 /* base of translation table entries */
#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin))
#define IIO_ITTE_OFFSET_BITS 5 /* size of offset field */
#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1)
#define IIO_ITTE_OFFSET_SHIFT 0
#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */
#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
#define IIO_ITTE_WIDGET_SHIFT 8
#define IIO_ITTE_IOSP 1 /* I/O Space bit */
#define IIO_ITTE_IOSP_MASK 1
#define IIO_ITTE_IOSP_SHIFT 12
#define HUB_PIO_MAP_TO_MEM 0
#define HUB_PIO_MAP_TO_IO 1
#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */
#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
(((((addr) >> BWIN_SIZE_BITS) & \
IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
(io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
(((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
#define IIO_ITTE_DISABLE(nasid, bigwin) \
IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
(bigwin), IIO_ITTE_INVALID_WIDGET, 0)
#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
/*
* Macro which takes the widget number, and returns the
* IO PRB address of that widget.
* value _x is expected to be a widget number in the range
* 0, 8 - 0xF
*/
#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
(_x) : \
(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
#endif /* _ASM_SN_IO_H */
include/asm-mips/sn/ioc3.h
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include/asm-mips/sn/klconfig.h
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include/asm-mips/sn/kldir.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
*
* Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 1999, 2000 by Ralf Baechle
*/
#ifndef _ASM_SN_KLDIR_H
#define _ASM_SN_KLDIR_H
#include <linux/config.h>
#if defined(CONFIG_SGI_IO)
#include <asm/hack.h>
#endif
/*
* The kldir memory area resides at a fixed place in each node's memory and
* provides pointers to most other IP27 memory areas. This allows us to
* resize and/or relocate memory areas at a later time without breaking all
* firmware and kernels that use them. Indices in the array are
* permanently dedicated to areas listed below. Some memory areas (marked
* below) reside at a permanently fixed location, but are included in the
* directory for completeness.
*/
#define KLDIR_MAGIC 0x434d5f53505f5357
/*
* The upper portion of the memory map applies during boot
* only and is overwritten by IRIX/SYMMON.
*
* MEMORY MAP PER NODE
*
* 0x2000000 (32M) +-----------------------------------------+
* | IO6 BUFFERS FOR FLASH ENET IOC3 |
* 0x1F80000 (31.5M) +-----------------------------------------+
* | IO6 TEXT/DATA/BSS/stack |
* 0x1C00000 (30M) +-----------------------------------------+
* | IO6 PROM DEBUG TEXT/DATA/BSS/stack |
* 0x0800000 (28M) +-----------------------------------------+
* | IP27 PROM TEXT/DATA/BSS/stack |
* 0x1B00000 (27M) +-----------------------------------------+
* | IP27 CFG |
* 0x1A00000 (26M) +-----------------------------------------+
* | Graphics PROM |
* 0x1800000 (24M) +-----------------------------------------+
* | 3rd Party PROM drivers |
* 0x1600000 (22M) +-----------------------------------------+
* | |
* | Free |
* | |
* +-----------------------------------------+
* | UNIX DEBUG Version |
* 0x190000 (2M--) +-----------------------------------------+
* | SYMMON |
* | (For UNIX Debug only) |
* 0x34000 (208K) +-----------------------------------------+
* | SYMMON STACK [NUM_CPU_PER_NODE] |
* | (For UNIX Debug only) |
* 0x25000 (148K) +-----------------------------------------+
* | KLCONFIG - II (temp) |
* | |
* | ---------------------------- |
* | |
* | UNIX NON-DEBUG Version |
* 0x19000 (100K) +-----------------------------------------+
*
*
* The lower portion of the memory map contains information that is
* permanent and is used by the IP27PROM, IO6PROM and IRIX.
*
* 0x19000 (100K) +-----------------------------------------+
* | |
* | PI Error Spools (32K) |
* | |
* 0x12000 (72K) +-----------------------------------------+
* | Unused |
* 0x11c00 (71K) +-----------------------------------------+
* | CPU 1 NMI Eframe area |
* 0x11a00 (70.5K) +-----------------------------------------+
* | CPU 0 NMI Eframe area |
* 0x11800 (70K) +-----------------------------------------+
* | CPU 1 NMI Register save area |
* 0x11600 (69.5K) +-----------------------------------------+
* | CPU 0 NMI Register save area |
* 0x11400 (69K) +-----------------------------------------+
* | GDA (1k) |
* 0x11000 (68K) +-----------------------------------------+
* | Early cache Exception stack |
* | and/or |
* | kernel/io6prom nmi registers |
* 0x10800 (66k) +-----------------------------------------+
* | cache error eframe |
* 0x10400 (65K) +-----------------------------------------+
* | Exception Handlers (UALIAS copy) |
* 0x10000 (64K) +-----------------------------------------+
* | |
* | |
* | KLCONFIG - I (permanent) (48K) |
* | |
* | |
* | |
* 0x4000 (16K) +-----------------------------------------+
* | NMI Handler (Protected Page) |
* 0x3000 (12K) +-----------------------------------------+
* | ARCS PVECTORS (master node only) |
* 0x2c00 (11K) +-----------------------------------------+
* | ARCS TVECTORS (master node only) |
* 0x2800 (10K) +-----------------------------------------+
* | LAUNCH [NUM_CPU] |
* 0x2400 (9K) +-----------------------------------------+
* | Low memory directory (KLDIR) |
* 0x2000 (8K) +-----------------------------------------+
* | ARCS SPB (1K) |
* 0x1000 (4K) +-----------------------------------------+
* | Early cache Exception stack |
* | and/or |
* | kernel/io6prom nmi registers |
* 0x800 (2k) +-----------------------------------------+
* | cache error eframe |
* 0x400 (1K) +-----------------------------------------+
* | Exception Handlers |
* 0x0 (0K) +-----------------------------------------+
*/
#ifdef __ASSEMBLY__
#define KLDIR_OFF_MAGIC 0x00
#define KLDIR_OFF_OFFSET 0x08
#define KLDIR_OFF_POINTER 0x10
#define KLDIR_OFF_SIZE 0x18
#define KLDIR_OFF_COUNT 0x20
#define KLDIR_OFF_STRIDE 0x28
#endif /* __ASSEMBLY__ */
#if !defined(CONFIG_SGI_IO)
/*
* This is defined here because IP27_SYMMON_STK_SIZE must be at least what
* we define here. Since it's set up in the prom. We can't redefine it later
* and expect more space to be allocated. The way to find out the true size
* of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
* for a particular node.
*/
#define SYMMON_STACK_SIZE 0x8000
#if defined (PROM) || defined (SABLE)
/*
* These defines are prom version dependent. No code other than the IP27
* prom should attempt to use these values.
*/
#define IP27_LAUNCH_OFFSET 0x2400
#define IP27_LAUNCH_SIZE 0x400
#define IP27_LAUNCH_COUNT 2
#define IP27_LAUNCH_STRIDE 0x200
#define IP27_KLCONFIG_OFFSET 0x4000
#define IP27_KLCONFIG_SIZE 0xc000
#define IP27_KLCONFIG_COUNT 1
#define IP27_KLCONFIG_STRIDE 0
#define IP27_NMI_OFFSET 0x3000
#define IP27_NMI_SIZE 0x40
#define IP27_NMI_COUNT 2
#define IP27_NMI_STRIDE 0x40
#define IP27_PI_ERROR_OFFSET 0x12000
#define IP27_PI_ERROR_SIZE 0x4000
#define IP27_PI_ERROR_COUNT 1
#define IP27_PI_ERROR_STRIDE 0
#define IP27_SYMMON_STK_OFFSET 0x25000
#define IP27_SYMMON_STK_SIZE 0xe000
#define IP27_SYMMON_STK_COUNT 2
/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
#define IP27_SYMMON_STK_STRIDE 0x7000
#define IP27_FREEMEM_OFFSET 0x19000
#define IP27_FREEMEM_SIZE -1
#define IP27_FREEMEM_COUNT 1
#define IP27_FREEMEM_STRIDE 0
#endif /* PROM || SABLE*/
/*
* There will be only one of these in a partition so the IO6 must set it up.
*/
#define IO6_GDA_OFFSET 0x11000
#define IO6_GDA_SIZE 0x400
#define IO6_GDA_COUNT 1
#define IO6_GDA_STRIDE 0
/*
* save area of kernel nmi regs in the prom format
*/
#define IP27_NMI_KREGS_OFFSET 0x11400
#define IP27_NMI_KREGS_CPU_SIZE 0x200
/*
* save area of kernel nmi regs in eframe format
*/
#define IP27_NMI_EFRAME_OFFSET 0x11800
#define IP27_NMI_EFRAME_SIZE 0x200
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
#endif /* !CONFIG_SGI_IO */
#ifndef __ASSEMBLY__
typedef struct kldir_ent_s {
u64 magic; /* Indicates validity of entry */
off_t offset; /* Offset from start of node space */
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t pointer; /* Pointer to area in some cases */
#else
unsigned long pointer; /* Pointer to area in some cases */
#endif
size_t size; /* Size in bytes */
u64 count; /* Repeat count if array, 1 if not */
size_t stride; /* Stride if array, 0 if not */
char rsvd[16]; /* Pad entry to 0x40 bytes */
/* NOTE: These 16 bytes are used in the Partition KLDIR
entry to store partition info. Refer to klpart.h for this. */
} kldir_ent_t;
#endif /* !__ASSEMBLY__ */
#if defined(CONFIG_SGI_IO)
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
/*
* The actual offsets of each memory area are machine-dependent
*/
#ifdef CONFIG_SGI_IP27
// Not yet #include <asm/sn/sn0/kldir.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/kldir.h>
#else
#error "kldir.h is currently defined for IP27 and IP35 platforms only"
#endif
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLDIR_H */
include/asm-mips/sn/klkernvars.h
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/*
* File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
* Copyright 2000 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_KLKERNVARS_H
#define __ASM_SN_KLKERNVARS_H
#define KV_MAGIC_OFFSET 0x0
#define KV_RO_NASID_OFFSET 0x4
#define KV_RW_NASID_OFFSET 0x6
#define KV_MAGIC 0x5f4b565f
#ifndef __ASSEMBLY__
#include <asm/sn/types.h>
typedef struct kern_vars_s {
int kv_magic;
nasid_t kv_ro_nasid;
nasid_t kv_rw_nasid;
unsigned long kv_ro_baseaddr;
unsigned long kv_rw_baseaddr;
} kern_vars_t;
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_SN_KLKERNVARS_H */
include/asm-mips/sn/launch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
* Copyright (C) 2000 by Colin Ngam
*/
#ifndef _ASM_SN_LAUNCH_H
#define _ASM_SN_LAUNCH_H
#include <linux/config.h>
#include <asm/sn/types.h>
#include <asm/sn/addrs.h>
/*
* The launch data structure resides at a fixed place in each node's memory
* and is used to communicate between the master processor and the slave
* processors.
*
* The master stores launch parameters in the launch structure
* corresponding to a target processor that is in a slave loop, then sends
* an interrupt to the slave processor. The slave calls the desired
* function, then returns to the slave loop. The master may poll or wait
* for the slaves to finish.
*
* There is an array of launch structures, one per CPU on the node. One
* interrupt level is used per local CPU.
*/
#define LAUNCH_MAGIC 0xaddbead2addbead3
#ifdef CONFIG_SGI_IP27
#define LAUNCH_SIZEOF 0x100
#define LAUNCH_PADSZ 0xa0
#endif
#define LAUNCH_OFF_MAGIC 0x00 /* Struct offsets for assembly */
#define LAUNCH_OFF_BUSY 0x08
#define LAUNCH_OFF_CALL 0x10
#define LAUNCH_OFF_CALLC 0x18
#define LAUNCH_OFF_CALLPARM 0x20
#define LAUNCH_OFF_STACK 0x28
#define LAUNCH_OFF_GP 0x30
#define LAUNCH_OFF_BEVUTLB 0x38
#define LAUNCH_OFF_BEVNORMAL 0x40
#define LAUNCH_OFF_BEVECC 0x48
#define LAUNCH_STATE_DONE 0 /* Return value of LAUNCH_POLL */
#define LAUNCH_STATE_SENT 1
#define LAUNCH_STATE_RECD 2
/*
* The launch routine is called only if the complement address is correct.
*
* Before control is transferred to a routine, the complement address
* is zeroed (invalidated) to prevent an accidental call from a spurious
* interrupt.
*
* The slave_launch routine turns on the BUSY flag, and the slave loop
* clears the BUSY flag after control is returned to it.
*/
#ifndef __ASSEMBLY__
typedef int launch_state_t;
typedef void (*launch_proc_t)(u64 call_parm);
typedef struct launch_s {
volatile u64 magic; /* Magic number */
volatile u64 busy; /* Slave currently active */
volatile launch_proc_t call_addr; /* Func. for slave to call */
volatile u64 call_addr_c; /* 1's complement of call_addr*/
volatile u64 call_parm; /* Single parm passed to call*/
volatile void *stack_addr; /* Stack pointer for slave function */
volatile void *gp_addr; /* Global pointer for slave func. */
volatile char *bevutlb;/* Address of bev utlb ex handler */
volatile char *bevnormal;/*Address of bev normal ex handler */
volatile char *bevecc;/* Address of bev cache err handler */
volatile char pad[160]; /* Pad to LAUNCH_SIZEOF */
} launch_t;
/*
* PROM entry points for launch routines are determined by IPxxprom/start.s
*/
#define LAUNCH_SLAVE (*(void (*)(int nasid, int cpu, \
launch_proc_t call_addr, \
u64 call_parm, \
void *stack_addr, \
void *gp_addr)) \
IP27PROM_LAUNCHSLAVE)
#define LAUNCH_WAIT (*(void (*)(int nasid, int cpu, int timeout_msec)) \
IP27PROM_WAITSLAVE)
#define LAUNCH_POLL (*(launch_state_t (*)(int nasid, int cpu)) \
IP27PROM_POLLSLAVE)
#define LAUNCH_LOOP (*(void (*)(void)) \
IP27PROM_SLAVELOOP)
#define LAUNCH_FLASH (*(void (*)(void)) \
IP27PROM_FLASHLEDS)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_SN_LAUNCH_H */
include/asm-mips/sn/mapped_kernel.h
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/*
* File created by Kanoj Sarcar 06/06/00.
* Copyright 2000 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_MAPPED_KERNEL_H
#define __ASM_SN_MAPPED_KERNEL_H
/*
* Note on how mapped kernels work: the text and data section is
* compiled at cksseg segment (LOADADDR = 0xc001c000), and the
* init/setup/data section gets a 16M virtual address bump in the
* ld.script file (so that tlblo0 and tlblo1 maps the sections).
* The vmlinux.64 section addresses are put in the xkseg range
* using the change-addresses makefile option. Use elfdump -of
* on IRIX to see where the sections go. The Origin loader loads
* the two sections contiguously in physical memory. The loader
* sets the entry point into kernel_entry using a xkphys address,
* but instead of using 0xa800000001160000, it uses the address
* 0xa800000000160000, which is where it physically loaded that
* code. So no jumps can be done before we have switched to using
* cksseg addresses.
*/
#include <linux/config.h>
#include <asm/addrspace.h>
#ifdef CONFIG_BUILD_ELF64
#define REP_BASE CAC_BASE
#else
#define REP_BASE CKSEG0
#endif
#ifdef CONFIG_MAPPED_KERNEL
#define MAPPED_ADDR_RO_TO_PHYS(x) (x - REP_BASE)
#define MAPPED_ADDR_RW_TO_PHYS(x) (x - REP_BASE - 16777216)
#define MAPPED_KERN_RO_PHYSBASE(n) \
(PLAT_NODE_DATA(n)->kern_vars.kv_ro_baseaddr)
#define MAPPED_KERN_RW_PHYSBASE(n) \
(PLAT_NODE_DATA(n)->kern_vars.kv_rw_baseaddr)
#define MAPPED_KERN_RO_TO_PHYS(x) \
((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid()))
#define MAPPED_KERN_RW_TO_PHYS(x) \
((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid()))
#else /* CONFIG_MAPPED_KERNEL */
#define MAPPED_KERN_RO_TO_PHYS(x) (x - REP_BASE)
#define MAPPED_KERN_RW_TO_PHYS(x) (x - REP_BASE)
#endif /* CONFIG_MAPPED_KERNEL */
#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
#endif /* __ASM_SN_MAPPED_KERNEL_H */
include/asm-mips/sn/nmi.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
*/
#ifndef __ASM_SN_NMI_H
#define __ASM_SN_NMI_H
#ident "$Revision: 1.5 $"
#include <asm/sn/addrs.h>
/*
* The launch data structure resides at a fixed place in each node's memory
* and is used to communicate between the master processor and the slave
* processors.
*
* The master stores launch parameters in the launch structure
* corresponding to a target processor that is in a slave loop, then sends
* an interrupt to the slave processor. The slave calls the desired
* function, followed by an optional rendezvous function, then returns to
* the slave loop. The master does not wait for the slaves before
* returning.
*
* There is an array of launch structures, one per CPU on the node. One
* interrupt level is used per CPU.
*/
#define NMI_MAGIC 0x48414d4d455201
#define NMI_SIZEOF 0x40
#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */
#define NMI_OFF_FLAGS 0x08
#define NMI_OFF_CALL 0x10
#define NMI_OFF_CALLC 0x18
#define NMI_OFF_CALLPARM 0x20
#define NMI_OFF_GMASTER 0x28
/*
* The NMI routine is called only if the complement address is
* correct.
*
* Before control is transferred to a routine, the complement address
* is zeroed (invalidated) to prevent an accidental call from a spurious
* interrupt.
*
*/
#ifndef __ASSEMBLY__
typedef struct nmi_s {
volatile unsigned long magic; /* Magic number */
volatile unsigned long flags; /* Combination of flags above */
volatile void *call_addr; /* Routine for slave to call */
volatile void *call_addr_c; /* 1's complement of address */
volatile void *call_parm; /* Single parm passed to call */
volatile unsigned long gmaster; /* Flag true only on global master*/
} nmi_t;
#endif /* !__ASSEMBLY__ */
/* Following definitions are needed both in the prom & the kernel
* to identify the format of the nmi cpu register save area in the
* low memory on each node.
*/
#ifndef __ASSEMBLY__
struct reg_struct {
unsigned long gpr[32];
unsigned long sr;
unsigned long cause;
unsigned long epc;
unsigned long badva;
unsigned long error_epc;
unsigned long cache_err;
unsigned long nmi_sr;
};
#endif /* !__ASSEMBLY__ */
/* These are the assembly language offsets into the reg_struct structure */
#define R0_OFF 0x0
#define R1_OFF 0x8
#define R2_OFF 0x10
#define R3_OFF 0x18
#define R4_OFF 0x20
#define R5_OFF 0x28
#define R6_OFF 0x30
#define R7_OFF 0x38
#define R8_OFF 0x40
#define R9_OFF 0x48
#define R10_OFF 0x50
#define R11_OFF 0x58
#define R12_OFF 0x60
#define R13_OFF 0x68
#define R14_OFF 0x70
#define R15_OFF 0x78
#define R16_OFF 0x80
#define R17_OFF 0x88
#define R18_OFF 0x90
#define R19_OFF 0x98
#define R20_OFF 0xa0
#define R21_OFF 0xa8
#define R22_OFF 0xb0
#define R23_OFF 0xb8
#define R24_OFF 0xc0
#define R25_OFF 0xc8
#define R26_OFF 0xd0
#define R27_OFF 0xd8
#define R28_OFF 0xe0
#define R29_OFF 0xe8
#define R30_OFF 0xf0
#define R31_OFF 0xf8
#define SR_OFF 0x100
#define CAUSE_OFF 0x108
#define EPC_OFF 0x110
#define BADVA_OFF 0x118
#define ERROR_EPC_OFF 0x120
#define CACHE_ERR_OFF 0x128
#define NMISR_OFF 0x130
#endif /* __ASM_SN_NMI_H */
include/asm-mips/sn/sn0/addrs.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_ADDRS_H
#define _ASM_SN_SN0_ADDRS_H
#include <linux/config.h>
/*
* SN0 (on a T5) Address map
*
* This file contains a set of definitions and macros which are used
* to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
* and UNCAC) used by the SN0 architecture. It also contains addresses
* for "major" statically locatable PROM/Kernel data structures, such as
* the partition table, the configuration data structure, etc.
* We make an implicit assumption that the processor using this file
* follows the R10K's provisions for specifying uncached attributes;
* should this change, the base registers may very well become processor-
* dependent.
*
* For more information on the address spaces, see the "Local Resources"
* chapter of the Hub specification.
*
* NOTE: This header file is included both by C and by assembler source
* files. Please bracket any language-dependent definitions
* appropriately.
*/
/*
* Some of the macros here need to be casted to appropriate types when used
* from C. They definitely must not be casted from assembly language so we
* use some new ANSI preprocessor stuff to paste these on where needed.
*/
/*
* The following couple of definitions will eventually need to be variables,
* since the amount of address space assigned to each node depends on
* whether the system is running in N-mode (more nodes with less memory)
* or M-mode (fewer nodes with more memory). We expect that it will
* be a while before we need to make this decision dynamically, though,
* so for now we just use defines bracketed by an ifdef.
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#define NODE_SIZE_BITS 31
#define BWIN_SIZE_BITS 28
#define NASID_BITS 9
#define NASID_BITMASK (0x1ffLL)
#define NASID_SHFT 31
#define NASID_META_BITS 5
#define NASID_LOCAL_BITS 4
#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
#define NODE_SIZE_BITS 32
#define BWIN_SIZE_BITS 29
#define NASID_BITMASK (0xffLL)
#define NASID_BITS 8
#define NASID_SHFT 32
#define NASID_META_BITS 4
#define NASID_LOCAL_BITS 4
#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
NASID_SHFT) & NASID_BITMASK)
#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
#define NODE_SWIN_BASE(nasid, widget) \
((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
: RAW_NODE_SWIN_BASE(nasid, widget))
#else /* __ASSEMBLY__ || _STANDALONE */
#define NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
#endif /* __ASSEMBLY__ || _STANDALONE */
/*
* The following definitions pertain to the IO special address
* space. They define the location of the big and little windows
* of any given node.
*/
#define BWIN_INDEX_BITS 3
#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
#define BWIN_SIZEMASK (BWIN_SIZE - 1)
#define BWIN_WIDGET_MASK 0x7
#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
(UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
/*
* Verify if addr belongs to large window address of node with "nasid"
*
*
* NOTE: "addr" is expected to be XKPHYS address, and NOT physical
* address
*
*
*/
#define NODE_BWIN_ADDR(nasid, addr) \
(((addr) >= NODE_BWIN_BASE0(nasid)) && \
((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
BWIN_SIZE)))
/*
* The following define the major position-independent aliases used
* in SN0.
* CALIAS -- Varies in size, points to the first n bytes of memory
* on the reader's node.
*/
#define CALIAS_BASE CAC_BASE
#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
/* Turn on sable logging for the processors whose bits are set. */
#ifdef SABLE
#define SABLE_LOG_TRIGGER(_map) \
*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
#else
#define SABLE_LOG_TRIGGER(_map)
#endif /* SABLE */
#ifndef __ASSEMBLY__
#define KERN_NMI_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
(IP27_NMI_KREGS_CPU_SIZE * (slice)))
#endif /* !__ASSEMBLY__ */
#ifdef PROM
#define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
#define MISC_PROM_SIZE 0x200000
#define DIAG_BASE PHYS_TO_K0(0x01500000)
#define DIAG_SIZE 0x300000
#define ROUTE_BASE PHYS_TO_K0(0x01800000)
#define ROUTE_SIZE 0x200000
#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
#define IP27PROM_CORP_MAX 32
#define IP27PROM_CORP PHYS_TO_K0(0x01800000)
#define IP27PROM_CORP_SIZE 0x10000
#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
#define IP27PROM_CORP_STKSIZE 0x2000
#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
#define IP27PROM_DECOMP_SIZE 0xfff00
#define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
#define IP27PROM_SIZE_MAX 0x100000
#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
#define IP27PROM_PCFG_SIZE 0xd0000
#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
#define IP27PROM_ERRDMP_SIZE 0xf000
#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
#define IP27PROM_CONSOLE_SIZE 0x200
#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
#define IP27PROM_NETUART_SIZE 0x100
#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
#define IP27PROM_UNUSED1_SIZE 0x500
#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
#define IP27PROM_STACK_SHFT 16
#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT)
#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
#define SLAVESTACK_SIZE 0x40000
#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
#define ENETBUFS_SIZE 0x20000
#define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
#define IO6PROM_SIZE 0x400000
#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
#define IO6DPROM_SIZE 0x200000
#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
#define IP27PROM_INT_LAUNCH 10 /* and 11 */
#define IP27PROM_INT_NETUART 12 /* through 17 */
#endif /* PROM */
/*
* needed by symmon so it needs to be outside #if PROM
*/
#define IP27PROM_ELSC_SHFT 10
#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
/*
* This address is used by IO6PROM to build MemoryDescriptors of
* free memory. This address is important since unix gets loaded
* at this address, and this memory has to be FREE if unix is to
* be loaded.
*/
#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
#define IO6PROM_STACK_SHFT 14 /* stack per cpu */
#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
/*
* IP27 PROM vectors
*/
#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */
#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */
#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
#define KL_I2C_REG MD_UREG0_0 /* I2C reg */
#ifndef __ASSEMBLY__
/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
* CACHE_ERR_SP_PTR could either contain an address to the stack, or
* the stack could start at CACHE_ERR_SP_PTR
*/
#if defined (HUB_ERR_STS_WAR)
#define CACHE_ERR_EFRAME 0x480
#else /* HUB_ERR_STS_WAR */
#define CACHE_ERR_EFRAME 0x400
#endif /* HUB_ERR_STS_WAR */
#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
#endif /* !__ASSEMBLY__ */
#define _ARCSPROM
#ifdef _STANDALONE
/*
* The PROM needs to pass the device base address and the
* device pci cfg space address to the device drivers during
* install. The COMPONENT->Key field is used for this purpose.
* Macros needed by SN0 device drivers to convert the
* COMPONENT->Key field to the respective base address.
* Key field looks as follows:
*
* +----------------------------------------------------+
* |devnasid | widget |pciid |hubwidid|hstnasid | adap |
* | 2 | 1 | 1 | 1 | 2 | 1 |
* +----------------------------------------------------+
* | | | | | | |
* 64 48 40 32 24 8 0
*
* These are used by standalone drivers till the io infrastructure
* is in place.
*/
#ifndef __ASSEMBLY__
#define uchar unsigned char
#define KEY_DEVNASID_SHFT 48
#define KEY_WIDID_SHFT 40
#define KEY_PCIID_SHFT 32
#define KEY_HUBWID_SHFT 24
#define KEY_HSTNASID_SHFT 8
#define MK_SN0_KEY(nasid, widid, pciid) \
((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
#define ADD_HUBWID_KEY(key,hubwid)\
(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
#define ADD_HSTNASID_KEY(key,hstnasid)\
(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
#define PCI_64_TARGID_SHFT 60
#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
#define GET_PCICFGBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
#define GET_WIDBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key)))
#define PUT_INSTALL_STATUS(c,s) c->Revision = s
#define GET_INSTALL_STATUS(c) c->Revision
#endif /* !__ASSEMBLY__ */
#endif /* _STANDALONE */
#if defined (HUB_ERR_STS_WAR)
#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
/* Used to match addr in error reg. */
#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
#endif /* HUB_ERR_STS_WAR */
#endif /* _ASM_SN_SN0_ADDRS_H */
include/asm-mips/sn/sn0/arch.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI IP27 specific setup.
*
* Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_SN_SN0_ARCH_H
#define _ASM_SN_SN0_ARCH_H
#include <linux/config.h>
#ifndef SABLE
#ifndef SN0XXL /* 128 cpu SMP max */
/*
* This is the maximum number of nodes that can be part of a kernel.
* Effectively, it's the maximum number of compact node ids (cnodeid_t).
*/
#define MAX_COMPACT_NODES 64
/*
* MAXCPUS refers to the maximum number of CPUs in a single kernel.
* This is not necessarily the same as MAXNODES * CPUS_PER_NODE
*/
#define MAXCPUS 128
#else /* SN0XXL system */
#define MAX_COMPACT_NODES 128
#define MAXCPUS 256
#endif /* SN0XXL */
/*
* This is the maximum number of NASIDS that can be present in a system.
* (Highest NASID plus one.)
*/
#define MAX_NASIDS 256
/*
* MAX_REGIONS refers to the maximum number of hardware partitioned regions.
*/
#define MAX_REGIONS 64
#define MAX_NONPREMIUM_REGIONS 16
#define MAX_PREMIUM_REGIONS MAX_REGIONS
/*
* MAX_PARITIONS refers to the maximum number of logically defined
* partitions the system can support.
*/
#define MAX_PARTITIONS MAX_REGIONS
#else
#define MAX_COMPACT_NODES 4
#define MAX_NASIDS 4
#define MAXCPUS 8
#endif
#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
/*
* Slot constants for SN0
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#define MAX_MEM_SLOTS 16 /* max slots per node */
#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
#define MAX_MEM_SLOTS 32 /* max slots per node */
#endif /* defined(N_MODE) */
#if SABLE_RTL
#define SLOT_SHIFT (28)
#define SLOT_MIN_MEM_SIZE (16*1024*1024)
#else
#define SLOT_SHIFT (27)
#define SLOT_MIN_MEM_SIZE (32*1024*1024)
#endif
#define CPUS_PER_NODE 2 /* CPUs on a single hub */
#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */
#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */
#endif /* _ASM_SN_SN0_ARCH_H */
include/asm-mips/sn/sn0/hub.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_HUB_H
#define _ASM_SN_SN0_HUB_H
/* The secret password; used to release protection */
#define HUB_PASSWORD 0x53474972756c6573ull
#define CHIPID_HUB 0
#define CHIPID_ROUTER 1
#define HUB_REV_1_0 1
#define HUB_REV_2_0 2
#define HUB_REV_2_1 3
#define HUB_REV_2_2 4
#define HUB_REV_2_3 5
#define HUB_REV_2_4 6
#define MAX_HUB_PATH 80
#include <asm/sn/sn0/addrs.h>
#include <asm/sn/sn0/hubpi.h>
#include <asm/sn/sn0/hubmd.h>
#include <asm/sn/sn0/hubio.h>
#include <asm/sn/sn0/hubni.h>
//#include <asm/sn/sn0/hubcore.h>
#ifdef SABLE
#define IP27_NO_HUBUART_INT 1
#endif
/* Translation of uncached attributes */
#define UATTR_HSPEC 0
#define UATTR_IO 1
#define UATTR_MSPEC 2
#define UATTR_UNCAC 3
#endif /* _ASM_SN_SN0_HUB_H */
include/asm-mips/sn/sn0/hubio.h
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include/asm-mips/sn/sn0/hubmd.h
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include/asm-mips/sn/sn0/hubni.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
*
* Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SGI_SN0_HUBNI_H
#define _ASM_SGI_SN0_HUBNI_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#endif
/*
* Hub Network Interface registers
*
* All registers in this file are subject to change until Hub chip tapeout.
*/
#define NI_BASE 0x600000
#define NI_BASE_TABLES 0x630000
#define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */
#define NI_PORT_RESET 0x600008 /* Reset the network interface */
#define NI_PROTECTION 0x600010 /* NI register access permissions */
#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */
#define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */
#define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */
#define NI_DIAG_PARMS 0x600110 /* Parameters for diags */
#define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
#define NI_VECTOR 0x600208 /* Vector PIO route */
#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
#define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
#define NI_IO_PROTECT 0x600400 /* PIO protection bits */
#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */
#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */
#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */
#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */
#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */
#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */
#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */
#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
#define NI_AGE_REG_MAX NI_AGE_IO_PIO
#define NI_PORT_PARMS 0x608000 /* LLP Parameters */
#define NI_PORT_ERROR 0x608008 /* LLP Errors */
#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */
#define NI_META_TABLE0 0x638000 /* First meta routing table entry */
#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
#define NI_META_ENTRIES 32
#define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */
#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
#define NI_LOCAL_ENTRIES 16
/*
* NI_STATUS_REV_ID mask and shift definitions
* Have to use UINT64_CAST instead of 'L' suffix, for assembler.
*/
#define NSRI_8BITMODE_SHFT 30
#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
#define NSRI_LINKUP_SHFT 29
#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
#define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */
#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
#define NSRI_MORENODES_SHFT 18
#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */
#define MORE_MEMORY 0
#define MORE_NODES 1
#define NSRI_REGIONSIZE_SHFT 17
#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */
#define REGIONSIZE_FINE 1
#define REGIONSIZE_COARSE 0
#define NSRI_NODEID_SHFT 8
#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
#define NSRI_REV_SHFT 4
#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
#define NSRI_CHIPID_SHFT 0
#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
/*
* In fine mode, each node is a region. In coarse mode, there are
* eight nodes per region.
*/
#define NASID_TO_FINEREG_SHFT 0
#define NASID_TO_COARSEREG_SHFT 3
/* NI_PORT_RESET mask definitions */
#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
/* NI_PROTECTION mask and shift definitions */
#define NPROT_RESETOK (UINT64_CAST 1)
/* NI_GLOBAL_PARMS mask and shift definitions */
#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */
#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */
#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */
#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */
#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
/* NI_DIAG_PARMS mask and shift definitions */
#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */
#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */
#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */
#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */
/*
* NI_VECTOR_PARMS mask and shift definitions.
* TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
*/
#define NVP_PIOID_SHFT 40
#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVP_WRITEID_SHFT 32
#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
#define NVP_TYPE_SHFT 0
#define NVP_TYPE_MASK (UINT64_CAST 0x3)
/* NI_VECTOR_STATUS mask and shift definitions */
#define NVS_VALID (UINT64_CAST 1 << 63)
#define NVS_OVERRUN (UINT64_CAST 1 << 62)
#define NVS_TARGET_SHFT 51
#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
#define NVS_PIOID_SHFT 40
#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVS_WRITEID_SHFT 32
#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
#define NVS_TYPE_SHFT 0
#define NVS_TYPE_MASK (UINT64_CAST 0x7)
#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */
#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */
#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */
#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */
#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */
/* NI_AGE_XXX mask and shift definitions */
#define NAGE_VCH_SHFT 10
#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
#define NAGE_CC_SHFT 8
#define NAGE_CC_MASK (UINT64_CAST 3 << 8)
#define NAGE_AGE_SHFT 0
#define NAGE_AGE_MASK (UINT64_CAST 0xff)
#define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
#define VCHANNEL_A 0
#define VCHANNEL_B 1
#define VCHANNEL_ANY 2
/* NI_PORT_PARMS mask and shift definitions */
#define NPP_NULLTO_SHFT 10
#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
#define NPP_MAXBURST_SHFT 0
#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \
(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \
(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
/* NI_PORT_ERROR mask and shift definitions */
#define NPE_LINKRESET (UINT64_CAST 1 << 37)
#define NPE_INTERNALERROR (UINT64_CAST 1 << 36)
#define NPE_BADMESSAGE (UINT64_CAST 1 << 35)
#define NPE_BADDEST (UINT64_CAST 1 << 34)
#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33)
#define NPE_CREDITTO_SHFT 28
#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
#define NPE_TAILTO_SHFT 24
#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
#define NPE_RETRYCOUNT_SHFT 16
#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
#define NPE_CBERRCOUNT_SHFT 8
#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
#define NPE_SNERRCOUNT_SHFT 0
#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
#define NPE_MASK 0x3effffffff
#define NPE_COUNT_MAX 0xff
#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \
NPE_BADMESSAGE | NPE_BADDEST | \
NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
NPE_TAILTO_MASK)
/* NI_META_TABLE mask and shift definitions */
#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
/* NI_LOCAL_TABLE mask and shift definitions */
#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
#ifndef __ASSEMBLY__
typedef union hubni_port_error_u {
u64 nipe_reg_value;
struct {
u64 nipe_rsvd: 26, /* unused */
nipe_lnk_reset: 1, /* link reset */
nipe_intl_err: 1, /* internal error */
nipe_bad_msg: 1, /* bad message */
nipe_bad_dest: 1, /* bad dest */
nipe_fifo_ovfl: 1, /* fifo overflow */
nipe_rsvd1: 1, /* unused */
nipe_credit_to: 4, /* credit timeout */
nipe_tail_to: 4, /* tail timeout */
nipe_retry_cnt: 8, /* retry error count */
nipe_cb_cnt: 8, /* checkbit error count */
nipe_sn_cnt: 8; /* sequence number count */
} nipe_fields_s;
} hubni_port_error_t;
#define NI_LLP_RETRY_MAX 0xff
#define NI_LLP_CB_MAX 0xff
#define NI_LLP_SN_MAX 0xff
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_SGI_SN0_HUBNI_H */

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