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[MIPS] IRQ cleanups
This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
committed by
Ralf Baechle
Ralf Baechle
parent
c87b6ebaea
commit
1603b5aca4
+20
-113
@@ -113,12 +113,6 @@ static void inline flush_mace_bus(void)
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* is quite different anyway.
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*/
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/*
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* IRQ spinlock - Ralf says not to disable CPU interrupts,
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* and I think he knows better.
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*/
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static DEFINE_SPINLOCK(ip32_irq_lock);
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/* Some initial interrupts to set up */
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extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
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extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
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@@ -138,12 +132,6 @@ static void enable_cpu_irq(unsigned int irq)
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set_c0_status(STATUSF_IP7);
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}
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static unsigned int startup_cpu_irq(unsigned int irq)
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{
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enable_cpu_irq(irq);
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return 0;
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}
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static void disable_cpu_irq(unsigned int irq)
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{
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clear_c0_status(STATUSF_IP7);
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@@ -155,16 +143,12 @@ static void end_cpu_irq(unsigned int irq)
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enable_cpu_irq (irq);
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}
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#define shutdown_cpu_irq disable_cpu_irq
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#define mask_and_ack_cpu_irq disable_cpu_irq
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static struct irq_chip ip32_cpu_interrupt = {
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.typename = "IP32 CPU",
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.startup = startup_cpu_irq,
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.shutdown = shutdown_cpu_irq,
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.enable = enable_cpu_irq,
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.disable = disable_cpu_irq,
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.ack = mask_and_ack_cpu_irq,
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.ack = disable_cpu_irq,
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.mask = disable_cpu_irq,
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.mask_ack = disable_cpu_irq,
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.unmask = enable_cpu_irq,
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.end = end_cpu_irq,
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};
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@@ -177,45 +161,27 @@ static uint64_t crime_mask;
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static void enable_crime_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_mask |= 1 << (irq - 1);
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crime->imask = crime_mask;
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static unsigned int startup_crime_irq(unsigned int irq)
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{
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enable_crime_irq(irq);
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return 0; /* This is probably not right; we could have pending irqs */
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}
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static void disable_crime_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_mask &= ~(1 << (irq - 1));
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crime->imask = crime_mask;
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flush_crime_bus();
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static void mask_and_ack_crime_irq(unsigned int irq)
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{
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unsigned long flags;
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/* Edge triggered interrupts must be cleared. */
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if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
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|| (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
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|| (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
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uint64_t crime_int;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_int = crime->hard_int;
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crime_int &= ~(1 << (irq - 1));
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crime->hard_int = crime_int;
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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disable_crime_irq(irq);
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}
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@@ -226,15 +192,12 @@ static void end_crime_irq(unsigned int irq)
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enable_crime_irq(irq);
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}
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#define shutdown_crime_irq disable_crime_irq
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static struct irq_chip ip32_crime_interrupt = {
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.typename = "IP32 CRIME",
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.startup = startup_crime_irq,
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.shutdown = shutdown_crime_irq,
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.enable = enable_crime_irq,
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.disable = disable_crime_irq,
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.ack = mask_and_ack_crime_irq,
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.mask = disable_crime_irq,
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.mask_ack = mask_and_ack_crime_irq,
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.unmask = enable_crime_irq,
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.end = end_crime_irq,
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};
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@@ -248,34 +211,20 @@ static unsigned long macepci_mask;
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static void enable_macepci_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
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mace->pci.control = macepci_mask;
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crime_mask |= 1 << (irq - 1);
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crime->imask = crime_mask;
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static unsigned int startup_macepci_irq(unsigned int irq)
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{
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enable_macepci_irq (irq);
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return 0;
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}
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static void disable_macepci_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_mask &= ~(1 << (irq - 1));
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crime->imask = crime_mask;
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flush_crime_bus();
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macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
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mace->pci.control = macepci_mask;
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flush_mace_bus();
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static void end_macepci_irq(unsigned int irq)
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@@ -284,16 +233,12 @@ static void end_macepci_irq(unsigned int irq)
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enable_macepci_irq(irq);
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}
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#define shutdown_macepci_irq disable_macepci_irq
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#define mask_and_ack_macepci_irq disable_macepci_irq
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static struct irq_chip ip32_macepci_interrupt = {
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.typename = "IP32 MACE PCI",
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.startup = startup_macepci_irq,
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.shutdown = shutdown_macepci_irq,
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.enable = enable_macepci_irq,
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.disable = disable_macepci_irq,
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.ack = mask_and_ack_macepci_irq,
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.ack = disable_macepci_irq,
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.mask = disable_macepci_irq,
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.mask_ack = disable_macepci_irq,
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.unmask = enable_macepci_irq,
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.end = end_macepci_irq,
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};
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@@ -339,7 +284,6 @@ static unsigned long maceisa_mask;
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static void enable_maceisa_irq (unsigned int irq)
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{
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unsigned int crime_int = 0;
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unsigned long flags;
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DBG ("maceisa enable: %u\n", irq);
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@@ -355,26 +299,16 @@ static void enable_maceisa_irq (unsigned int irq)
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break;
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}
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DBG ("crime_int %08x enabled\n", crime_int);
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_mask |= crime_int;
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crime->imask = crime_mask;
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maceisa_mask |= 1 << (irq - 33);
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mace->perif.ctrl.imask = maceisa_mask;
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static unsigned int startup_maceisa_irq(unsigned int irq)
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{
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enable_maceisa_irq(irq);
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return 0;
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}
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static void disable_maceisa_irq(unsigned int irq)
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{
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unsigned int crime_int = 0;
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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maceisa_mask &= ~(1 << (irq - 33));
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if(!(maceisa_mask & MACEISA_AUDIO_INT))
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crime_int |= MACE_AUDIO_INT;
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@@ -387,23 +321,20 @@ static void disable_maceisa_irq(unsigned int irq)
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flush_crime_bus();
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mace->perif.ctrl.imask = maceisa_mask;
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flush_mace_bus();
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static void mask_and_ack_maceisa_irq(unsigned int irq)
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{
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unsigned long mace_int, flags;
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unsigned long mace_int;
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switch (irq) {
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case MACEISA_PARALLEL_IRQ:
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case MACEISA_SERIAL1_TDMAPR_IRQ:
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case MACEISA_SERIAL2_TDMAPR_IRQ:
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/* edge triggered */
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spin_lock_irqsave(&ip32_irq_lock, flags);
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mace_int = mace->perif.ctrl.istat;
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mace_int &= ~(1 << (irq - 33));
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mace->perif.ctrl.istat = mace_int;
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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break;
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}
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disable_maceisa_irq(irq);
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@@ -415,15 +346,12 @@ static void end_maceisa_irq(unsigned irq)
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enable_maceisa_irq(irq);
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}
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#define shutdown_maceisa_irq disable_maceisa_irq
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static struct irq_chip ip32_maceisa_interrupt = {
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.typename = "IP32 MACE ISA",
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.startup = startup_maceisa_irq,
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.shutdown = shutdown_maceisa_irq,
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.enable = enable_maceisa_irq,
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.disable = disable_maceisa_irq,
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.ack = mask_and_ack_maceisa_irq,
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.mask = disable_maceisa_irq,
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.mask_ack = mask_and_ack_maceisa_irq,
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.unmask = enable_maceisa_irq,
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.end = end_maceisa_irq,
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};
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@@ -433,29 +361,15 @@ static struct irq_chip ip32_maceisa_interrupt = {
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static void enable_mace_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_mask |= 1 << (irq - 1);
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crime->imask = crime_mask;
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static unsigned int startup_mace_irq(unsigned int irq)
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{
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enable_mace_irq(irq);
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return 0;
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}
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static void disable_mace_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ip32_irq_lock, flags);
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crime_mask &= ~(1 << (irq - 1));
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crime->imask = crime_mask;
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flush_crime_bus();
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spin_unlock_irqrestore(&ip32_irq_lock, flags);
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}
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static void end_mace_irq(unsigned int irq)
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@@ -464,16 +378,12 @@ static void end_mace_irq(unsigned int irq)
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enable_mace_irq(irq);
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}
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#define shutdown_mace_irq disable_mace_irq
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#define mask_and_ack_mace_irq disable_mace_irq
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static struct irq_chip ip32_mace_interrupt = {
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.typename = "IP32 MACE",
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.startup = startup_mace_irq,
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.shutdown = shutdown_mace_irq,
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.enable = enable_mace_irq,
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.disable = disable_mace_irq,
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.ack = mask_and_ack_mace_irq,
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.ack = disable_mace_irq,
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.mask = disable_mace_irq,
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.mask_ack = disable_mace_irq,
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.unmask = enable_mace_irq,
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.end = end_mace_irq,
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};
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@@ -586,10 +496,7 @@ void __init arch_init_irq(void)
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else
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controller = &ip32_maceisa_interrupt;
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irq_desc[irq].status = IRQ_DISABLED;
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irq_desc[irq].action = 0;
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irq_desc[irq].depth = 0;
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irq_desc[irq].chip = controller;
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set_irq_chip(irq, controller);
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}
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setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
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setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
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