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ixgbe: Add hardware specific initialization code for 82599 devices
This patch adds the hardware initialization code specific to 82599. This is similar to the 82598 hardware initialization code. It also includes all changes to the existing hardware init code to support 82599. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
PJ Waskiewicz
committed by
David S. Miller
David S. Miller
parent
8010dc306b
commit
11afc1b1fd
@@ -1046,9 +1046,9 @@ out:
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*
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* Determines physical layer capabilities of the current configuration.
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**/
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static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
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static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
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{
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s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
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u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
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switch (hw->device_id) {
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case IXGBE_DEV_ID_82598:
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@@ -1111,8 +1111,11 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
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.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
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.get_media_type = &ixgbe_get_media_type_82598,
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.get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
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.enable_rx_dma = &ixgbe_enable_rx_dma_generic,
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.get_mac_addr = &ixgbe_get_mac_addr_generic,
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.stop_adapter = &ixgbe_stop_adapter_generic,
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.get_bus_info = &ixgbe_get_bus_info_generic,
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.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
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.read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
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.write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
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.setup_link = &ixgbe_setup_mac_link_82598,
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File diff suppressed because it is too large
Load Diff
@@ -29,6 +29,7 @@
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include "ixgbe.h"
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#include "ixgbe_common.h"
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#include "ixgbe_phy.h"
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@@ -250,6 +251,81 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
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return 0;
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}
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/**
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* ixgbe_get_bus_info_generic - Generic set PCI bus info
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* @hw: pointer to hardware structure
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*
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* Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
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**/
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s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
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{
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struct ixgbe_adapter *adapter = hw->back;
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struct ixgbe_mac_info *mac = &hw->mac;
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u16 link_status;
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hw->bus.type = ixgbe_bus_type_pci_express;
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/* Get the negotiated link width and speed from PCI config space */
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pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
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&link_status);
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switch (link_status & IXGBE_PCI_LINK_WIDTH) {
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case IXGBE_PCI_LINK_WIDTH_1:
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hw->bus.width = ixgbe_bus_width_pcie_x1;
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break;
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case IXGBE_PCI_LINK_WIDTH_2:
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hw->bus.width = ixgbe_bus_width_pcie_x2;
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break;
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case IXGBE_PCI_LINK_WIDTH_4:
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hw->bus.width = ixgbe_bus_width_pcie_x4;
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break;
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case IXGBE_PCI_LINK_WIDTH_8:
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hw->bus.width = ixgbe_bus_width_pcie_x8;
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break;
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default:
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hw->bus.width = ixgbe_bus_width_unknown;
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break;
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}
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switch (link_status & IXGBE_PCI_LINK_SPEED) {
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case IXGBE_PCI_LINK_SPEED_2500:
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hw->bus.speed = ixgbe_bus_speed_2500;
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break;
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case IXGBE_PCI_LINK_SPEED_5000:
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hw->bus.speed = ixgbe_bus_speed_5000;
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break;
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default:
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hw->bus.speed = ixgbe_bus_speed_unknown;
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break;
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}
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mac->ops.set_lan_id(hw);
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return 0;
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}
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/**
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* ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
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* @hw: pointer to the HW structure
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*
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* Determines the LAN function id by reading memory-mapped registers
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* and swaps the port value if requested.
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**/
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void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
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{
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struct ixgbe_bus_info *bus = &hw->bus;
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u32 reg;
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reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
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bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
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bus->lan_id = bus->func;
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/* check for a port swap */
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reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
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if (reg & IXGBE_FACTPS_LFS)
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bus->func ^= 0x1;
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}
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/**
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* ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
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* @hw: pointer to hardware structure
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@@ -389,6 +465,73 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
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return 0;
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}
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/**
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* ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
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* @hw: pointer to hardware structure
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* @offset: offset within the EEPROM to be written to
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* @data: 16 bit word to be written to the EEPROM
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*
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* If ixgbe_eeprom_update_checksum is not called after this function, the
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* EEPROM will most likely contain an invalid checksum.
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**/
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s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
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{
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s32 status;
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u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
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hw->eeprom.ops.init_params(hw);
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if (offset >= hw->eeprom.word_size) {
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status = IXGBE_ERR_EEPROM;
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goto out;
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}
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/* Prepare the EEPROM for writing */
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status = ixgbe_acquire_eeprom(hw);
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if (status == 0) {
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if (ixgbe_ready_eeprom(hw) != 0) {
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ixgbe_release_eeprom(hw);
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status = IXGBE_ERR_EEPROM;
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}
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}
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if (status == 0) {
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ixgbe_standby_eeprom(hw);
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/* Send the WRITE ENABLE command (8 bit opcode ) */
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ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
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IXGBE_EEPROM_OPCODE_BITS);
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ixgbe_standby_eeprom(hw);
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/*
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* Some SPI eeproms use the 8th address bit embedded in the
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* opcode
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*/
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if ((hw->eeprom.address_bits == 8) && (offset >= 128))
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write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
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/* Send the Write command (8-bit opcode + addr) */
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ixgbe_shift_out_eeprom_bits(hw, write_opcode,
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IXGBE_EEPROM_OPCODE_BITS);
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ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
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hw->eeprom.address_bits);
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/* Send the data */
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data = (data >> 8) | (data << 8);
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ixgbe_shift_out_eeprom_bits(hw, data, 16);
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ixgbe_standby_eeprom(hw);
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msleep(hw->eeprom.semaphore_delay);
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/* Done with writing - release the EEPROM */
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ixgbe_release_eeprom(hw);
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}
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out:
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return status;
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}
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/**
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* ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
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* @hw: pointer to hardware structure
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@@ -1486,6 +1629,101 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
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return 0;
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}
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/**
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* ixgbe_fc_enable - Enable flow control
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* @hw: pointer to hardware structure
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* @packetbuf_num: packet buffer number (0-7)
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*
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* Enable flow control according to the current settings.
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**/
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s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
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{
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s32 ret_val = 0;
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u32 mflcn_reg;
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u32 fccfg_reg;
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u32 reg;
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mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
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mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
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fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
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fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
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/*
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* The possible values of fc.current_mode are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames,
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* but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames but
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* we do not support receiving pause frames).
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* 3: Both Rx and Tx flow control (symmetric) are enabled.
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* other: Invalid.
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*/
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switch (hw->fc.current_mode) {
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case ixgbe_fc_none:
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/* Flow control completely disabled by software override. */
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break;
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case ixgbe_fc_rx_pause:
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/*
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* Rx Flow control is enabled and Tx Flow control is
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* disabled by software override. Since there really
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* isn't a way to advertise that we are capable of RX
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* Pause ONLY, we will advertise that we support both
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* symmetric and asymmetric Rx PAUSE. Later, we will
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* disable the adapter's ability to send PAUSE frames.
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*/
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mflcn_reg |= IXGBE_MFLCN_RFCE;
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break;
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case ixgbe_fc_tx_pause:
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/*
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* Tx Flow control is enabled, and Rx Flow control is
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* disabled by software override.
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*/
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fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
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break;
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case ixgbe_fc_full:
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/* Flow control (both Rx and Tx) is enabled by SW override. */
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mflcn_reg |= IXGBE_MFLCN_RFCE;
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fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
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break;
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default:
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hw_dbg(hw, "Flow control param set incorrectly\n");
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ret_val = -IXGBE_ERR_CONFIG;
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goto out;
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break;
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}
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/* Enable 802.3x based flow control settings. */
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IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
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IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
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/* Set up and enable Rx high/low water mark thresholds, enable XON. */
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if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
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if (hw->fc.send_xon)
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
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(hw->fc.low_water | IXGBE_FCRTL_XONE));
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else
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
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hw->fc.low_water);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
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(hw->fc.high_water | IXGBE_FCRTH_FCEN));
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}
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/* Configure pause time (2 TCs per register) */
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reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
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if ((packetbuf_num & 1) == 0)
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reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
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else
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reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
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out:
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return ret_val;
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}
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/**
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* ixgbe_fc_autoneg - Configure flow control
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* @hw: pointer to hardware structure
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@@ -1624,6 +1862,74 @@ out:
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return ret_val;
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}
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/**
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* ixgbe_setup_fc_generic - Set up flow control
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* @hw: pointer to hardware structure
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*
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* Sets up flow control.
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**/
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s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
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{
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s32 ret_val = 0;
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ixgbe_link_speed speed;
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bool link_up;
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/* Validate the packetbuf configuration */
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if (packetbuf_num < 0 || packetbuf_num > 7) {
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hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
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"is 0-7\n", packetbuf_num);
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ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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/*
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* Validate the water mark configuration. Zero water marks are invalid
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* because it causes the controller to just blast out fc packets.
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*/
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if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
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hw_dbg(hw, "Invalid water mark configuration\n");
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ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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/*
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* Validate the requested mode. Strict IEEE mode does not allow
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* ixgbe_fc_rx_pause because it will cause testing anomalies.
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*/
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if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
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hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
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"IEEE mode\n");
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ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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/*
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* 10gig parts do not have a word in the EEPROM to determine the
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* default flow control setting, so we explicitly set it to full.
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*/
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if (hw->fc.requested_mode == ixgbe_fc_default)
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hw->fc.requested_mode = ixgbe_fc_full;
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/*
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* Save off the requested flow control mode for use later. Depending
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* on the link partner's capabilities, we may or may not use this mode.
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*/
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hw->fc.current_mode = hw->fc.requested_mode;
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/* Decide whether to use autoneg or not. */
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hw->mac.ops.check_link(hw, &speed, &link_up, false);
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if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL))
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ret_val = ixgbe_fc_autoneg(hw);
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if (ret_val)
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goto out;
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ret_val = ixgbe_fc_enable(hw, packetbuf_num);
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out:
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return ret_val;
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}
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/**
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* ixgbe_disable_pcie_master - Disable PCI-express master access
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* @hw: pointer to hardware structure
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@@ -1732,3 +2038,16 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
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ixgbe_release_eeprom_semaphore(hw);
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}
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/**
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* ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
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* @hw: pointer to hardware structure
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* @regval: register value to write to RXCTRL
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*
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* Enables the Rx DMA unit
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**/
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s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
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{
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IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
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return 0;
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}
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@@ -37,12 +37,14 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
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s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
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s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
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s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
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void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
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s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
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s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
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s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
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s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
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s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
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u16 *data);
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@@ -61,6 +63,7 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
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u32 addr_count, ixgbe_mc_addr_itr func);
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s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
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s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
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s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
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s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num);
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s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packtetbuf_num);
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s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
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@@ -75,6 +78,13 @@ s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
|
||||
|
||||
#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
|
||||
|
||||
#ifndef writeq
|
||||
#define writeq(val, addr) writel((u32) (val), addr); \
|
||||
writel((u32) (val >> 32), (addr + 4));
|
||||
#endif
|
||||
|
||||
#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
|
||||
|
||||
#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
|
||||
|
||||
#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
|
||||
|
||||
@@ -469,7 +469,7 @@ static void ixgbe_get_regs(struct net_device *netdev,
|
||||
regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
|
||||
regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
|
||||
regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
|
||||
regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT);
|
||||
regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
|
||||
|
||||
regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
|
||||
regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -54,14 +54,15 @@
|
||||
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
|
||||
|
||||
/* Bit-shift macros */
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
|
||||
|
||||
/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
|
||||
#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
|
||||
#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
|
||||
#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
|
||||
#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
|
||||
|
||||
/* I2C SDA and SCL timing parameters for standard mode */
|
||||
#define IXGBE_I2C_T_HD_STA 4
|
||||
@@ -101,5 +102,12 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
|
||||
u16 *list_offset,
|
||||
u16 *data_offset);
|
||||
|
||||
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 *data);
|
||||
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 data);
|
||||
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 *eeprom_data);
|
||||
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 eeprom_data);
|
||||
#endif /* _IXGBE_PHY_H_ */
|
||||
|
||||
+719
-29
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user