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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.7. Here's the summary of
the changes:
- ATH79: Support for DTB passuing using the UHI boot protocol
- ATH79: Remove support for builtin DTB.
- ATH79: Add zboot debug serial support.
- ATH79: Add initial support for Dragino MS14 (Dragine 2), Onion Omega
and DPT-Module.
- ATH79: Update devicetree clock support for AR9132 and AR9331.
- ATH79: Cleanup the DT code.
- ATH79: Support newer SOCs in ath79_ddr_ctrl_init.
- ATH79: Fix regression in PCI window initialization.
- BCM47xx: Move SPROM driver to drivers/firmware/
- BCM63xx: Enable partition parser in defconfig.
- BMIPS: BMIPS5000 has I cache filing from D cache
- BMIPS: BMIPS: Add cpu-feature-overrides.h
- BMIPS: Add Whirlwind support
- BMIPS: Adjust mips-hpt-frequency for BCM7435
- BMIPS: Remove maxcpus from BCM97435SVMB DTS
- BMIPS: Add missing 7038 L1 register cells to BCM7435
- BMIPS: Various tweaks to initialization code.
- BMIPS: Enable partition parser in defconfig.
- BMIPS: Cache tweaks.
- BMIPS: Add UART, I2C and SATA devices to DT.
- BMIPS: Add BCM6358 and BCM63268support
- BMIPS: Add device tree example for BCM6358.
- BMIPS: Improve Improve BCM6328 and BCM6368 device trees
- Lantiq: Add support for device tree file from boot loader
- Lantiq: Allow build with no built-in DT.
- Loongson 3: Reserve 32MB for RS780E integrated GPU.
- Loongson 3: Fix build error after ld-version.sh modification
- Loongson 3: Move chipset ACPI code from drivers to arch.
- Loongson 3: Speedup irq processing.
- Loongson 3: Add basic Loongson 3A support.
- Loongson 3: Set cache flush handlers to nop.
- Loongson 3: Invalidate special TLBs when needed.
- Loongson 3: Fast TLB refill handler.
- MT7620: Fallback strategy for invalid syscfg0.
- Netlogic: Fix CP0_EBASE redefinition warnings
- Octeon: Initialization fixes
- Octeon: Add DTS files for the D-Link DSR-1000N and EdgeRouter Lite
- Octeon: Enable add Octeon-drivers in cavium_octeon_defconfig
- Octeon: Correctly handle endian-swapped initramfs images.
- Octeon: Support CN73xx, CN75xx and CN78xx.
- Octeon: Remove dead code from cvmx-sysinfo.
- Octeon: Extend number of supported CPUs past 32.
- Octeon: Remove some code limiting NR_IRQS to 255.
- Octeon: Simplify octeon_irq_ciu_gpio_set_type.
- Octeon: Mark some functions __init in smp.c
- Octeon: Octeon: Add Octeon III CN7xxx interface detection
- PIC32: Add serial driver and bindings for it.
- PIC32: Add PIC32 deadman timer driver and bindings.
- PIC32: Add PIC32 clock timer driver and bindings.
- Pistachio: Determine SoC revision during boot
- Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHER.
- Sibyte: Strip redundant comments from bcm1480_regs.h.
- Panic immediately if panic_on_oops is set.
- module: fix incorrect IS_ERR_VALUE macro usage.
- module: Make consistent use of pr_*
- Remove no longer needed work_on_cpu() call.
- Remove CONFIG_IPV6_PRIVACY from defconfigs.
- Fix registers of non-crashing CPUs in dumps.
- Handle MIPSisms in new vmcore_elf32_check_arch.
- Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.
- Allow RIXI to be used on non-R2 or R6 cores.
- Reserve nosave data for hibernation
- Fix siginfo.h to use strict POSIX types.
- Don't unwind user mode with EVA.
- Fix watchpoint restoration
- Ptrace watchpoints for R6.
- Sync icache when it fills from dcache
- I6400 I-cache fills from dcache.
- Various MSA fixes.
- Cleanup MIPS_CPU_* definitions.
- Signal: Move generic copy_siginfo to signal.h
- Signal: Fix uapi include in exported asm/siginfo.h
- Timer fixes for sake of KVM.
- XPA TLB refill fixes.
- Treat perf counter feature
- Update John Crispin's email address
- Add PIC32 watchdog and bindings.
- Handle R10000 LL/SC bug in set_pte()
- cpufreq: Various fixes for Longson1.
- R6: Fix R2 emulation.
- mathemu: Cosmetic fix to ADDIUPC emulation, plenty of other small fixes
- ELF: ABI and FP fixes.
- Allow for relocatable kernel and use that to support KASLR.
- Fix CPC_BASE_ADDR mask
- Plenty fo smp-cps, CM, R6 and M6250 fixes.
- Make reset_control_ops const.
- Fix kernel command line handling of leading whitespace.
- Cleanups to cache handling.
- Add brcm, bcm6345-l1-intc device tree bindings.
- Use generic clkdev.h header
- Remove CLK_IS_ROOT usage.
- Misc small cleanups.
- CM: Fix compilation error when !MIPS_CM
- oprofile: Fix a preemption issue
- Detect DSP ASE v3 support:1"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (275 commits)
MIPS: pic32mzda: fix getting timer clock rate.
MIPS: ath79: fix regression in PCI window initialization
MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs
MIPS: Fix VZ probe gas errors with binutils <2.24
MIPS: perf: Fix I6400 event numbers
MIPS: DEC: Export `ioasic_ssr_lock' to modules
MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC
MIPS: CM: Fix compilation error when !MIPS_CM
MIPS: Fix genvdso error on rebuild
USB: ohci-jz4740: Remove obsolete driver
MIPS: JZ4740: Probe OHCI platform device via DT
MIPS: JZ4740: Qi LB60: Remove support for AVT2 variant
MIPS: pistachio: Determine SoC revision during boot
MIPS: BMIPS: Adjust mips-hpt-frequency for BCM7435
mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type
MIPS: Prevent "restoration" of MSA context in non-MSA kernels
MIPS: cevt-r4k: Dynamically calculate min_delta_ns
MIPS: malta-time: Take seconds into account
MIPS: malta-time: Start GIC count before syncing to RTC
MIPS: Force CPUs to lose FP context during mode switches
...
This commit is contained in:
Linus Torvalds
@@ -15,10 +15,6 @@ menuconfig MIPS_PLATFORM_DEVICES
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if MIPS_PLATFORM_DEVICES
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config MIPS_ACPI
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bool
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default y if LOONGSON_MACH3X
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config CPU_HWMON
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tristate "Loongson CPU HWMon Driver"
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depends on LOONGSON_MACH3X
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@@ -1,2 +1 @@
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obj-$(CONFIG_MIPS_ACPI) += acpi_init.o
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obj-$(CONFIG_CPU_HWMON) += cpu_hwmon.o
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@@ -1,150 +0,0 @@
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/export.h>
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#define SBX00_ACPI_IO_BASE 0x800
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#define SBX00_ACPI_IO_SIZE 0x100
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#define ACPI_PM_EVT_BLK (SBX00_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM_CNT_BLK (SBX00_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PMA_CNT_BLK (SBX00_ACPI_IO_BASE + 0x0F) /* 1 byte */
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#define ACPI_PM_TMR_BLK (SBX00_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_GPE0_BLK (SBX00_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_END (SBX00_ACPI_IO_BASE + 0x80)
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#define PM_INDEX 0xCD6
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#define PM_DATA 0xCD7
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#define PM2_INDEX 0xCD0
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#define PM2_DATA 0xCD1
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/*
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* SCI interrupt need acpi space, allocate here
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*/
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static int __init register_acpi_resource(void)
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{
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request_region(SBX00_ACPI_IO_BASE, SBX00_ACPI_IO_SIZE, "acpi");
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return 0;
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}
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static void pmio_write_index(u16 index, u8 reg, u8 value)
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{
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outb(reg, index);
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outb(value, index + 1);
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}
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static u8 pmio_read_index(u16 index, u8 reg)
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{
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outb(reg, index);
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return inb(index + 1);
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}
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void pm_iowrite(u8 reg, u8 value)
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{
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pmio_write_index(PM_INDEX, reg, value);
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}
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EXPORT_SYMBOL(pm_iowrite);
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u8 pm_ioread(u8 reg)
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{
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return pmio_read_index(PM_INDEX, reg);
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}
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EXPORT_SYMBOL(pm_ioread);
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void pm2_iowrite(u8 reg, u8 value)
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{
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pmio_write_index(PM2_INDEX, reg, value);
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}
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EXPORT_SYMBOL(pm2_iowrite);
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u8 pm2_ioread(u8 reg)
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{
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return pmio_read_index(PM2_INDEX, reg);
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}
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EXPORT_SYMBOL(pm2_ioread);
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static void acpi_hw_clear_status(void)
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{
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u16 value;
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/* PMStatus: Clear WakeStatus/PwrBtnStatus */
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value = inw(ACPI_PM_EVT_BLK);
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value |= (1 << 8 | 1 << 15);
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outw(value, ACPI_PM_EVT_BLK);
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/* GPEStatus: Clear all generated events */
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outl(inl(ACPI_GPE0_BLK), ACPI_GPE0_BLK);
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}
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void acpi_registers_setup(void)
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{
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u32 value;
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/* PM Status Base */
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pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xff);
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pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
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/* PM Control Base */
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pm_iowrite(0x22, ACPI_PM_CNT_BLK & 0xff);
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pm_iowrite(0x23, ACPI_PM_CNT_BLK >> 8);
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/* GPM Base */
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pm_iowrite(0x28, ACPI_GPE0_BLK & 0xff);
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pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
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/* ACPI End */
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pm_iowrite(0x2e, ACPI_END & 0xff);
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pm_iowrite(0x2f, ACPI_END >> 8);
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/* IO Decode: When AcpiDecodeEnable set, South-Bridge uses the contents
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* of the PM registers at index 0x20~0x2B to decode ACPI I/O address. */
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pm_iowrite(0x0e, 1 << 3);
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/* SCI_EN set */
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outw(1, ACPI_PM_CNT_BLK);
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/* Enable to generate SCI */
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pm_iowrite(0x10, pm_ioread(0x10) | 1);
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/* GPM3/GPM9 enable */
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value = inl(ACPI_GPE0_BLK + 4);
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outl(value | (1 << 14) | (1 << 22), ACPI_GPE0_BLK + 4);
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/* Set GPM9 as input */
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pm_iowrite(0x8d, pm_ioread(0x8d) & (~(1 << 1)));
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/* Set GPM9 as non-output */
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pm_iowrite(0x94, pm_ioread(0x94) | (1 << 3));
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/* GPM3 config ACPI trigger SCIOUT */
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pm_iowrite(0x33, pm_ioread(0x33) & (~(3 << 4)));
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/* GPM9 config ACPI trigger SCIOUT */
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pm_iowrite(0x3d, pm_ioread(0x3d) & (~(3 << 2)));
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/* GPM3 config falling edge trigger */
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pm_iowrite(0x37, pm_ioread(0x37) & (~(1 << 6)));
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/* No wait for STPGNT# in ACPI Sx state */
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pm_iowrite(0x7c, pm_ioread(0x7c) | (1 << 6));
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/* Set GPM3 pull-down enable */
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value = pm2_ioread(0xf6);
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value |= ((1 << 7) | (1 << 3));
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pm2_iowrite(0xf6, value);
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/* Set GPM9 pull-down enable */
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value = pm2_ioread(0xf8);
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value |= ((1 << 5) | (1 << 1));
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pm2_iowrite(0xf8, value);
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}
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int __init sbx00_acpi_init(void)
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{
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register_acpi_resource();
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acpi_registers_setup();
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acpi_hw_clear_status();
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return 0;
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}
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@@ -20,9 +20,9 @@ int loongson3_cpu_temp(int cpu)
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u32 reg;
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reg = LOONGSON_CHIPTEMP(cpu);
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if (loongson_sysconf.cputype == Loongson_3A)
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if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1)
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reg = (reg >> 8) & 0xff;
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else if (loongson_sysconf.cputype == Loongson_3B)
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else
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reg = ((reg >> 8) & 0xff) - 100;
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return (int)reg * 1000;
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