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Merge tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
* tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: (29 commits) C6X: replace tick_nohz_stop/restart_sched_tick calls C6X: add register_cpu call C6X: deal with memblock API changes C6X: fix timer64 initialization C6X: fix layout of EMIFA registers C6X: MAINTAINERS C6X: DSCR - Device State Configuration Registers C6X: EMIF - External Memory Interface C6X: general SoC support C6X: library code C6X: headers C6X: ptrace support C6X: loadable module support C6X: cache control C6X: clocks C6X: build infrastructure C6X: syscalls C6X: interrupt handling C6X: time management C6X: signal management ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,40 @@
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C6X PLL Clock Controllers
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-------------------------
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This is a first-cut support for the SoC clock controllers. This is still
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under development and will probably change as the common device tree
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clock support is added to the kernel.
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Required properties:
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- compatible: "ti,c64x+pll"
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May also have SoC-specific value to support SoC-specific initialization
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in the driver. One of:
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"ti,c6455-pll"
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"ti,c6457-pll"
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"ti,c6472-pll"
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"ti,c6474-pll"
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- reg: base address and size of register area
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- clock-frequency: input clock frequency in hz
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Optional properties:
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- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
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- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
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- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
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Example:
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clock-controller@29a0000 {
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compatible = "ti,c6472-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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clock-frequency = <25000000>;
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ti,c64x+pll-bypass-delay = <200>;
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ti,c64x+pll-reset-delay = <12000>;
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ti,c64x+pll-lock-delay = <80000>;
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};
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@@ -0,0 +1,127 @@
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Device State Configuration Registers
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------------------------------------
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TI C6X SoCs contain a region of miscellaneous registers which provide various
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function for SoC control or status. Details vary considerably among from SoC
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to SoC with no two being alike.
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In general, the Device State Configuraion Registers (DSCR) will provide one or
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more configuration registers often protected by a lock register where one or
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more key values must be written to a lock register in order to unlock the
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configuration register for writes. These configuration register may be used to
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enable (and disable in some cases) SoC pin drivers, select peripheral clock
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sources (internal or pin), etc. In some cases, a configuration register is
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write once or the individual bits are write once. In addition to device config,
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the DSCR block may provide registers which which are used to reset peripherals,
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provide device ID information, provide ethernet MAC addresses, as well as other
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miscellaneous functions.
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For device state control (enable/disable), each device control is assigned an
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id which is used by individual device drivers to control the state as needed.
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Required properties:
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- compatible: must be "ti,c64x+dscr"
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- reg: register area base and size
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Optional properties:
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NOTE: These are optional in that not all SoCs will have all properties. For
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SoCs which do support a given property, leaving the property out of the
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device tree will result in reduced functionality or possibly driver
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failure.
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- ti,dscr-devstat
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offset of the devstat register
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- ti,dscr-silicon-rev
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offset, start bit, and bitsize of silicon revision field
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- ti,dscr-rmii-resets
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offset and bitmask of RMII reset field. May have multiple tuples if more
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than one ethernet port is available.
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- ti,dscr-locked-regs
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possibly multiple tuples describing registers which are write protected by
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a lock register. Each tuple consists of the register offset, lock register
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offsset, and the key value used to unlock the register.
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- ti,dscr-kick-regs
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offset and key values of two "kick" registers used to write protect other
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registers in DSCR. On SoCs using kick registers, the first key must be
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written to the first kick register and the second key must be written to
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the second register before other registers in the area are write-enabled.
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- ti,dscr-mac-fuse-regs
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MAC addresses are contained in two registers. Each element of a MAC address
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is contained in a single byte. This property has two tuples. Each tuple has
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a register offset and four cells representing bytes in the register from
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most significant to least. The value of these four cells is the MAC byte
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index (1-6) of the byte within the register. A value of 0 means the byte
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is unused in the MAC address.
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- ti,dscr-devstate-ctl-regs
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This property describes the bitfields used to control the state of devices.
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Each tuple describes a range of identical bitfields used to control one or
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more devices (one bitfield per device). The layout of each tuple is:
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start_id num_ids reg enable disable start_bit nbits
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Where:
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start_id is device id for the first device control in the range
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num_ids is the number of device controls in the range
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reg is the offset of the register holding the control bits
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enable is the value to enable a device
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disable is the value to disable a device (0xffffffff if cannot disable)
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start_bit is the bit number of the first bit in the range
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nbits is the number of bits per device control
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- ti,dscr-devstate-stat-regs
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This property describes the bitfields used to provide device state status
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for device states controlled by the DSCR. Each tuple describes a range of
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identical bitfields used to provide status for one or more devices (one
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bitfield per device). The layout of each tuple is:
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start_id num_ids reg enable disable start_bit nbits
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Where:
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start_id is device id for the first device status in the range
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num_ids is the number of devices covered by the range
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reg is the offset of the register holding the status bits
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enable is the value indicating device is enabled
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disable is the value indicating device is disabled
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start_bit is the bit number of the first bit in the range
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nbits is the number of bits per device status
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- ti,dscr-privperm
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Offset and default value for register used to set access privilege for
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some SoC devices.
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Example:
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device-state-config-regs@2a80000 {
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compatible = "ti,c64x+dscr";
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reg = <0x02a80000 0x41000>;
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ti,dscr-devstat = <0>;
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ti,dscr-silicon-rev = <8 28 0xf>;
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ti,dscr-rmii-resets = <0x40020 0x00040000>;
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ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
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ti,dscr-devstate-ctl-regs =
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<0 12 0x40008 1 0 0 2
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12 1 0x40008 3 0 30 2
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13 2 0x4002c 1 0xffffffff 0 1>;
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ti,dscr-devstate-stat-regs =
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<0 10 0x40014 1 0 0 3
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10 2 0x40018 1 0 0 3>;
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ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
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0x704 5 6 0 0>;
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ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
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ti,dscr-kick-regs = <0x38 0x83E70B13
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0x3c 0x95A4F1E0>;
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};
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@@ -0,0 +1,62 @@
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External Memory Interface
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-------------------------
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The emifa node describes a simple external bus controller found on some C6X
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SoCs. This interface provides external busses with a number of chip selects.
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Required properties:
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- compatible: must be "ti,c64x+emifa", "simple-bus"
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- reg: register area base and size
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- #address-cells: must be 2 (chip-select + offset)
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- #size-cells: must be 1
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- ranges: mapping from EMIFA space to parent space
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Optional properties:
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- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
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- ti,emifa-burst-priority:
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Number of memory transfers after which the EMIF will elevate the priority
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of the oldest command in the command FIFO. Setting this field to 255
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disables this feature, thereby allowing old commands to stay in the FIFO
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indefinitely.
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- ti,emifa-ce-config:
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Configuration values for each of the supported chip selects.
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Example:
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emifa@70000000 {
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compatible = "ti,c64x+emifa", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x70000000 0x100>;
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ranges = <0x2 0x0 0xa0000000 0x00000008
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0x3 0x0 0xb0000000 0x00400000
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0x4 0x0 0xc0000000 0x10000000
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0x5 0x0 0xD0000000 0x10000000>;
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ti,dscr-dev-enable = <13>;
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ti,emifa-burst-priority = <255>;
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ti,emifa-ce-config = <0x00240120
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0x00240120
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0x00240122
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0x00240122>;
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flash@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x3 0x0 0x400000>;
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bank-width = <1>;
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device-width = <1>;
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partition@0 {
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reg = <0x0 0x400000>;
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label = "NOR";
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};
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};
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};
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This shows a flash chip attached to chip select 3.
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@@ -0,0 +1,104 @@
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C6X Interrupt Chips
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-------------------
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* C64X+ Core Interrupt Controller
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The core interrupt controller provides 16 prioritized interrupts to the
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C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
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Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
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sources coming from outside the core.
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Required properties:
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|
--------------------
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- compatible: Should be "ti,c64x+core-pic";
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- #interrupt-cells: <1>
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Interrupt Specifier Definition
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------------------------------
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Single cell specifying the core interrupt priority level (4-15) where
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4 is highest priority and 15 is lowest priority.
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Example
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|
-------
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core_pic: interrupt-controller@0 {
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interrupt-controller;
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|
#interrupt-cells = <1>;
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compatible = "ti,c64x+core-pic";
|
||||||
|
};
|
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|
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||||||
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* C64x+ Megamodule Interrupt Controller
|
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|
|
||||||
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The megamodule PIC consists of four interrupt mupliplexers each of which
|
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combine up to 32 interrupt inputs into a single interrupt output which
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may be cascaded into the core interrupt controller. The megamodule PIC
|
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has a total of 12 outputs cascading into the core interrupt controller.
|
||||||
|
One for each core interrupt priority level. In addition to the combined
|
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|
interrupt sources, individual megamodule interrupts may be cascaded to
|
||||||
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the core interrupt controller. When an individual interrupt is cascaded,
|
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it is no longer handled through a megamodule interrupt combiner and is
|
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|
considered to have the core interrupt controller as the parent.
|
||||||
|
|
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|
Required properties:
|
||||||
|
--------------------
|
||||||
|
- compatible: "ti,c64x+megamod-pic"
|
||||||
|
- interrupt-controller
|
||||||
|
- #interrupt-cells: <1>
|
||||||
|
- reg: base address and size of register area
|
||||||
|
- interrupt-parent: must be core interrupt controller
|
||||||
|
- interrupts: This should have four cells; one for each interrupt combiner.
|
||||||
|
The cells contain the core priority interrupt to which the
|
||||||
|
corresponding combiner output is wired.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
--------------------
|
||||||
|
- ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
|
||||||
|
priority interrupts. The first cell corresponds to
|
||||||
|
core priority 4 and the last cell corresponds to
|
||||||
|
core priority 15. The value of each cell is the
|
||||||
|
megamodule interrupt source which is MUXed to
|
||||||
|
the core interrupt corresponding to the cell
|
||||||
|
position. Allowed values are 4 - 127. Mapping for
|
||||||
|
interrupts 0 - 3 (combined interrupt sources) are
|
||||||
|
ignored.
|
||||||
|
|
||||||
|
Interrupt Specifier Definition
|
||||||
|
------------------------------
|
||||||
|
Single cell specifying the megamodule interrupt source (4-127). Note that
|
||||||
|
interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
|
||||||
|
use the core interrupt controller as their parent and the specifier will
|
||||||
|
be the core priority level, not the megamodule interrupt number.
|
||||||
|
|
||||||
|
Examples
|
||||||
|
--------
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
compatible = "ti,c64x+megamod-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
reg = <0x1800000 0x1000>;
|
||||||
|
interrupt-parent = <&core_pic>;
|
||||||
|
interrupts = < 12 13 14 15 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
This is a minimal example where all individual interrupts go through a
|
||||||
|
combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
|
||||||
|
to interrupt 13, etc.
|
||||||
|
|
||||||
|
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
compatible = "ti,c64x+megamod-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
reg = <0x1800000 0x1000>;
|
||||||
|
interrupt-parent = <&core_pic>;
|
||||||
|
interrupts = < 12 13 14 15 >;
|
||||||
|
ti,c64x+megamod-pic-mux = < 0 0 0 0
|
||||||
|
32 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
This the same as the first example except that megamodule interrupt 32 is
|
||||||
|
mapped directly to core priority interrupt 8. The node using this interrupt
|
||||||
|
must set the core controller as its interrupt parent and use 8 in the
|
||||||
|
interrupt specifier value.
|
||||||
@@ -0,0 +1,28 @@
|
|||||||
|
C6X System-on-Chip
|
||||||
|
------------------
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- compatible: "simple-bus"
|
||||||
|
- #address-cells: must be 1
|
||||||
|
- #size-cells: must be 1
|
||||||
|
- ranges
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
|
||||||
|
- model: specific SoC model
|
||||||
|
|
||||||
|
- nodes for IP blocks within SoC
|
||||||
|
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
model = "tms320c6455";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
...
|
||||||
|
};
|
||||||
@@ -0,0 +1,26 @@
|
|||||||
|
Timer64
|
||||||
|
-------
|
||||||
|
|
||||||
|
The timer64 node describes C6X event timers.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- compatible: must be "ti,c64x+timer64"
|
||||||
|
- reg: base address and size of register region
|
||||||
|
- interrupt-parent: interrupt controller
|
||||||
|
- interrupts: interrupt id
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
|
||||||
|
- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
|
||||||
|
|
||||||
|
- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
timer0: timer@25e0000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x01 >;
|
||||||
|
reg = <0x25e0000 0x40>;
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
@@ -1645,6 +1645,14 @@ T: git git://git.alsa-project.org/alsa-kernel.git
|
|||||||
S: Maintained
|
S: Maintained
|
||||||
F: sound/pci/oxygen/
|
F: sound/pci/oxygen/
|
||||||
|
|
||||||
|
C6X ARCHITECTURE
|
||||||
|
M: Mark Salter <msalter@redhat.com>
|
||||||
|
M: Aurelien Jacquiot <a-jacquiot@ti.com>
|
||||||
|
L: linux-c6x-dev@linux-c6x.org
|
||||||
|
W: http://www.linux-c6x.org/wiki/index.php/Main_Page
|
||||||
|
S: Maintained
|
||||||
|
F: arch/c6x/
|
||||||
|
|
||||||
CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
|
CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
|
||||||
M: David Howells <dhowells@redhat.com>
|
M: David Howells <dhowells@redhat.com>
|
||||||
L: linux-cachefs@redhat.com
|
L: linux-cachefs@redhat.com
|
||||||
|
|||||||
@@ -0,0 +1,174 @@
|
|||||||
|
#
|
||||||
|
# For a description of the syntax of this configuration file,
|
||||||
|
# see Documentation/kbuild/kconfig-language.txt.
|
||||||
|
#
|
||||||
|
|
||||||
|
config TMS320C6X
|
||||||
|
def_bool y
|
||||||
|
select CLKDEV_LOOKUP
|
||||||
|
select GENERIC_IRQ_SHOW
|
||||||
|
select HAVE_ARCH_TRACEHOOK
|
||||||
|
select HAVE_DMA_API_DEBUG
|
||||||
|
select HAVE_GENERIC_HARDIRQS
|
||||||
|
select HAVE_MEMBLOCK
|
||||||
|
select HAVE_SPARSE_IRQ
|
||||||
|
select OF
|
||||||
|
select OF_EARLY_FLATTREE
|
||||||
|
|
||||||
|
config MMU
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config ZONE_DMA
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config FPU
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config HIGHMEM
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config NUMA
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config RWSEM_GENERIC_SPINLOCK
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config RWSEM_XCHGADD_ALGORITHM
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config GENERIC_CALIBRATE_DELAY
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config GENERIC_HWEIGHT
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config GENERIC_CLOCKEVENTS
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config GENERIC_CLOCKEVENTS_BROADCAST
|
||||||
|
bool
|
||||||
|
|
||||||
|
config GENERIC_BUG
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config COMMON_CLKDEV
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config C6X_BIG_KERNEL
|
||||||
|
bool "Build a big kernel"
|
||||||
|
help
|
||||||
|
The C6X function call instruction has a limited range of +/- 2MiB.
|
||||||
|
This is sufficient for most kernels, but some kernel configurations
|
||||||
|
with lots of compiled-in functionality may require a larger range
|
||||||
|
for function calls. Use this option to have the compiler generate
|
||||||
|
function calls with 32-bit range. This will make the kernel both
|
||||||
|
larger and slower.
|
||||||
|
|
||||||
|
If unsure, say N.
|
||||||
|
|
||||||
|
source "init/Kconfig"
|
||||||
|
|
||||||
|
# Use the generic interrupt handling code in kernel/irq/
|
||||||
|
|
||||||
|
source "kernel/Kconfig.freezer"
|
||||||
|
|
||||||
|
config CMDLINE_BOOL
|
||||||
|
bool "Default bootloader kernel arguments"
|
||||||
|
|
||||||
|
config CMDLINE
|
||||||
|
string "Kernel command line"
|
||||||
|
depends on CMDLINE_BOOL
|
||||||
|
default "console=ttyS0,57600"
|
||||||
|
help
|
||||||
|
On some architectures there is currently no way for the boot loader
|
||||||
|
to pass arguments to the kernel. For these architectures, you should
|
||||||
|
supply some command-line options at build time by entering them
|
||||||
|
here.
|
||||||
|
|
||||||
|
config CMDLINE_FORCE
|
||||||
|
bool "Force default kernel command string"
|
||||||
|
depends on CMDLINE_BOOL
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Set this to have arguments from the default kernel command string
|
||||||
|
override those passed by the boot loader.
|
||||||
|
|
||||||
|
config CPU_BIG_ENDIAN
|
||||||
|
bool "Build big-endian kernel"
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Say Y if you plan on running a kernel in big-endian mode.
|
||||||
|
Note that your board must be properly built and your board
|
||||||
|
port must properly enable any big-endian related features
|
||||||
|
of your chipset/board/processor.
|
||||||
|
|
||||||
|
config FORCE_MAX_ZONEORDER
|
||||||
|
int "Maximum zone order"
|
||||||
|
default "13"
|
||||||
|
help
|
||||||
|
The kernel memory allocator divides physically contiguous memory
|
||||||
|
blocks into "zones", where each zone is a power of two number of
|
||||||
|
pages. This option selects the largest power of two that the kernel
|
||||||
|
keeps in the memory allocator. If you need to allocate very large
|
||||||
|
blocks of physically contiguous memory, then you may need to
|
||||||
|
increase this value.
|
||||||
|
|
||||||
|
This config option is actually maximum order plus one. For example,
|
||||||
|
a value of 11 means that the largest free memory block is 2^10 pages.
|
||||||
|
|
||||||
|
menu "Processor type and features"
|
||||||
|
|
||||||
|
source "arch/c6x/platforms/Kconfig"
|
||||||
|
|
||||||
|
config TMS320C6X_CACHES_ON
|
||||||
|
bool "L2 cache support"
|
||||||
|
default y
|
||||||
|
|
||||||
|
config KERNEL_RAM_BASE_ADDRESS
|
||||||
|
hex "Virtual address of memory base"
|
||||||
|
default 0xe0000000 if SOC_TMS320C6455
|
||||||
|
default 0xe0000000 if SOC_TMS320C6457
|
||||||
|
default 0xe0000000 if SOC_TMS320C6472
|
||||||
|
default 0x80000000
|
||||||
|
|
||||||
|
source "mm/Kconfig"
|
||||||
|
|
||||||
|
source "kernel/Kconfig.preempt"
|
||||||
|
|
||||||
|
source "kernel/Kconfig.hz"
|
||||||
|
source "kernel/time/Kconfig"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
menu "Executable file formats"
|
||||||
|
|
||||||
|
source "fs/Kconfig.binfmt"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
source "net/Kconfig"
|
||||||
|
|
||||||
|
source "drivers/Kconfig"
|
||||||
|
|
||||||
|
source "fs/Kconfig"
|
||||||
|
|
||||||
|
source "security/Kconfig"
|
||||||
|
|
||||||
|
source "crypto/Kconfig"
|
||||||
|
|
||||||
|
source "lib/Kconfig"
|
||||||
|
|
||||||
|
menu "Kernel hacking"
|
||||||
|
|
||||||
|
source "lib/Kconfig.debug"
|
||||||
|
|
||||||
|
config ACCESS_CHECK
|
||||||
|
bool "Check the user pointer address"
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
Usually the pointer transfer from user space is checked to see if its
|
||||||
|
address is in the kernel space.
|
||||||
|
|
||||||
|
Say N here to disable that check to improve the performance.
|
||||||
|
|
||||||
|
endmenu
|
||||||
@@ -0,0 +1,60 @@
|
|||||||
|
#
|
||||||
|
# linux/arch/c6x/Makefile
|
||||||
|
#
|
||||||
|
# This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
# License. See the file "COPYING" in the main directory of this archive
|
||||||
|
# for more details.
|
||||||
|
#
|
||||||
|
|
||||||
|
cflags-y += -mno-dsbt -msdata=none
|
||||||
|
|
||||||
|
cflags-$(CONFIG_C6X_BIG_KERNEL) += -mlong-calls
|
||||||
|
|
||||||
|
CFLAGS_MODULE += -mlong-calls -mno-dsbt -msdata=none
|
||||||
|
|
||||||
|
CHECKFLAGS +=
|
||||||
|
|
||||||
|
KBUILD_CFLAGS += $(cflags-y)
|
||||||
|
KBUILD_AFLAGS += $(cflags-y)
|
||||||
|
|
||||||
|
ifdef CONFIG_CPU_BIG_ENDIAN
|
||||||
|
KBUILD_CFLAGS += -mbig-endian
|
||||||
|
KBUILD_AFLAGS += -mbig-endian
|
||||||
|
LINKFLAGS += -mbig-endian
|
||||||
|
KBUILD_LDFLAGS += -mbig-endian
|
||||||
|
LDFLAGS += -EB
|
||||||
|
endif
|
||||||
|
|
||||||
|
head-y := arch/c6x/kernel/head.o
|
||||||
|
core-y += arch/c6x/kernel/ arch/c6x/mm/ arch/c6x/platforms/
|
||||||
|
libs-y += arch/c6x/lib/
|
||||||
|
|
||||||
|
# Default to vmlinux.bin, override when needed
|
||||||
|
all: vmlinux.bin
|
||||||
|
|
||||||
|
boot := arch/$(ARCH)/boot
|
||||||
|
|
||||||
|
# Are we making a dtbImage.<boardname> target? If so, crack out the boardname
|
||||||
|
DTB:=$(subst dtbImage.,,$(filter dtbImage.%, $(MAKECMDGOALS)))
|
||||||
|
export DTB
|
||||||
|
|
||||||
|
ifneq ($(DTB),)
|
||||||
|
core-y += $(boot)/
|
||||||
|
endif
|
||||||
|
|
||||||
|
# With make 3.82 we cannot mix normal and wildcard targets
|
||||||
|
|
||||||
|
vmlinux.bin: vmlinux
|
||||||
|
$(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
|
||||||
|
|
||||||
|
dtbImage.%: vmlinux
|
||||||
|
$(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
|
||||||
|
|
||||||
|
archclean:
|
||||||
|
$(Q)$(MAKE) $(clean)=$(boot)
|
||||||
|
|
||||||
|
define archhelp
|
||||||
|
@echo ' vmlinux.bin - Binary kernel image (arch/$(ARCH)/boot/vmlinux.bin)'
|
||||||
|
@echo ' dtbImage.<dt> - ELF image with $(arch)/boot/dts/<dt>.dts linked in'
|
||||||
|
@echo ' - stripped elf with fdt blob'
|
||||||
|
endef
|
||||||
@@ -0,0 +1,30 @@
|
|||||||
|
#
|
||||||
|
# Makefile for bootable kernel images
|
||||||
|
#
|
||||||
|
|
||||||
|
OBJCOPYFLAGS_vmlinux.bin := -O binary
|
||||||
|
$(obj)/vmlinux.bin: vmlinux FORCE
|
||||||
|
$(call if_changed,objcopy)
|
||||||
|
|
||||||
|
DTC_FLAGS ?= -p 1024
|
||||||
|
|
||||||
|
ifneq ($(DTB),)
|
||||||
|
obj-y += linked_dtb.o
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(obj)/%.dtb: $(src)/dts/%.dts FORCE
|
||||||
|
$(call cmd,dtc)
|
||||||
|
|
||||||
|
quiet_cmd_cp = CP $< $@$2
|
||||||
|
cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
|
||||||
|
|
||||||
|
# Generate builtin.dtb from $(DTB).dtb
|
||||||
|
$(obj)/builtin.dtb: $(obj)/$(DTB).dtb
|
||||||
|
$(call if_changed,cp)
|
||||||
|
|
||||||
|
$(obj)/linked_dtb.o: $(obj)/builtin.dtb
|
||||||
|
|
||||||
|
$(obj)/dtbImage.%: vmlinux
|
||||||
|
$(call if_changed,objcopy)
|
||||||
|
|
||||||
|
clean-files := $(obj)/*.dtb
|
||||||
@@ -0,0 +1,62 @@
|
|||||||
|
/*
|
||||||
|
* arch/c6x/boot/dts/dsk6455.dts
|
||||||
|
*
|
||||||
|
* DSK6455 Evaluation Platform For TMS320C6455
|
||||||
|
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||||
|
*
|
||||||
|
* Author: Mark Salter <msalter@redhat.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "tms320c6455.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Spectrum Digital DSK6455";
|
||||||
|
compatible = "spectrum-digital,dsk6455";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "root=/dev/nfs ip=dhcp rw";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0xE0000000 0x08000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
interrupts = < 12 13 14 15 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
emifa@70000000 {
|
||||||
|
flash@3,0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0x3 0x0 0x400000>;
|
||||||
|
bank-width = <1>;
|
||||||
|
device-width = <1>;
|
||||||
|
partition@0 {
|
||||||
|
reg = <0x0 0x400000>;
|
||||||
|
label = "NOR";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer1: timer@2980000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 69 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@029a0000 {
|
||||||
|
clock-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,48 @@
|
|||||||
|
/*
|
||||||
|
* arch/c6x/boot/dts/evmc6457.dts
|
||||||
|
*
|
||||||
|
* EVMC6457 Evaluation Platform For TMS320C6457
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||||
|
*
|
||||||
|
* Author: Mark Salter <msalter@redhat.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "tms320c6457.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "eInfochips EVMC6457";
|
||||||
|
compatible = "einfochips,evmc6457";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0xE0000000 0x10000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
interrupts = < 12 13 14 15 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer0: timer@2940000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 67 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@29a0000 {
|
||||||
|
clock-frequency = <60000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,73 @@
|
|||||||
|
/*
|
||||||
|
* arch/c6x/boot/dts/evmc6472.dts
|
||||||
|
*
|
||||||
|
* EVMC6472 Evaluation Platform For TMS320C6472
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||||
|
*
|
||||||
|
* Author: Mark Salter <msalter@redhat.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "tms320c6472.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "eInfochips EVMC6472";
|
||||||
|
compatible = "einfochips,evmc6472";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0xE0000000 0x10000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
interrupts = < 12 13 14 15 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer0: timer@25e0000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer1: timer@25f0000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer2: timer@2600000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3: timer@2610000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer4: timer@2620000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer5: timer@2630000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 16 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@29a0000 {
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,58 @@
|
|||||||
|
/*
|
||||||
|
* arch/c6x/boot/dts/evmc6474.dts
|
||||||
|
*
|
||||||
|
* EVMC6474 Evaluation Platform For TMS320C6474
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||||
|
*
|
||||||
|
* Author: Mark Salter <msalter@redhat.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "tms320c6474.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Spectrum Digital EVMC6474";
|
||||||
|
compatible = "spectrum-digital,evmc6474";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x80000000 0x08000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
interrupts = < 12 13 14 15 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3: timer@2940000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 39 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer4: timer@2950000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 41 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer5: timer@2960000 {
|
||||||
|
interrupt-parent = <&megamod_pic>;
|
||||||
|
interrupts = < 43 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@29a0000 {
|
||||||
|
clock-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,96 @@
|
|||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
model = "ti,c64x+";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
model = "tms320c6455";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
core_pic: interrupt-controller {
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
compatible = "ti,c64x+core-pic";
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Megamodule interrupt controller
|
||||||
|
*/
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
compatible = "ti,c64x+megamod-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
reg = <0x1800000 0x1000>;
|
||||||
|
interrupt-parent = <&core_pic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cache-controller@1840000 {
|
||||||
|
compatible = "ti,c64x+cache";
|
||||||
|
reg = <0x01840000 0x8400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
emifa@70000000 {
|
||||||
|
compatible = "ti,c64x+emifa", "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
reg = <0x70000000 0x100>;
|
||||||
|
ranges = <0x2 0x0 0xa0000000 0x00000008
|
||||||
|
0x3 0x0 0xb0000000 0x00400000
|
||||||
|
0x4 0x0 0xc0000000 0x10000000
|
||||||
|
0x5 0x0 0xD0000000 0x10000000>;
|
||||||
|
|
||||||
|
ti,dscr-dev-enable = <13>;
|
||||||
|
ti,emifa-burst-priority = <255>;
|
||||||
|
ti,emifa-ce-config = <0x00240120
|
||||||
|
0x00240120
|
||||||
|
0x00240122
|
||||||
|
0x00240122>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer1: timer@2980000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
reg = <0x2980000 0x40>;
|
||||||
|
ti,dscr-dev-enable = <4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@029a0000 {
|
||||||
|
compatible = "ti,c6455-pll", "ti,c64x+pll";
|
||||||
|
reg = <0x029a0000 0x200>;
|
||||||
|
ti,c64x+pll-bypass-delay = <1440>;
|
||||||
|
ti,c64x+pll-reset-delay = <15360>;
|
||||||
|
ti,c64x+pll-lock-delay = <24000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
device-state-config-regs@2a80000 {
|
||||||
|
compatible = "ti,c64x+dscr";
|
||||||
|
reg = <0x02a80000 0x41000>;
|
||||||
|
|
||||||
|
ti,dscr-devstat = <0>;
|
||||||
|
ti,dscr-silicon-rev = <8 28 0xf>;
|
||||||
|
ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
|
||||||
|
|
||||||
|
ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
|
||||||
|
ti,dscr-devstate-ctl-regs =
|
||||||
|
<0 12 0x40008 1 0 0 2
|
||||||
|
12 1 0x40008 3 0 30 2
|
||||||
|
13 2 0x4002c 1 0xffffffff 0 1>;
|
||||||
|
ti,dscr-devstate-stat-regs =
|
||||||
|
<0 10 0x40014 1 0 0 3
|
||||||
|
10 2 0x40018 1 0 0 3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,68 @@
|
|||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
model = "ti,c64x+";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
model = "tms320c6457";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
core_pic: interrupt-controller {
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
compatible = "ti,c64x+core-pic";
|
||||||
|
};
|
||||||
|
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
compatible = "ti,c64x+megamod-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-parent = <&core_pic>;
|
||||||
|
reg = <0x1800000 0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cache-controller@1840000 {
|
||||||
|
compatible = "ti,c64x+cache";
|
||||||
|
reg = <0x01840000 0x8400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
device-state-controller@2880800 {
|
||||||
|
compatible = "ti,c64x+dscr";
|
||||||
|
reg = <0x02880800 0x400>;
|
||||||
|
|
||||||
|
ti,dscr-devstat = <0x20>;
|
||||||
|
ti,dscr-silicon-rev = <0x18 28 0xf>;
|
||||||
|
ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
|
||||||
|
0x118 0 0 1 2>;
|
||||||
|
ti,dscr-kick-regs = <0x38 0x83E70B13
|
||||||
|
0x3c 0x95A4F1E0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer0: timer@2940000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
reg = <0x2940000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@29a0000 {
|
||||||
|
compatible = "ti,c6457-pll", "ti,c64x+pll";
|
||||||
|
reg = <0x029a0000 0x200>;
|
||||||
|
ti,c64x+pll-bypass-delay = <300>;
|
||||||
|
ti,c64x+pll-reset-delay = <24000>;
|
||||||
|
ti,c64x+pll-lock-delay = <50000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,134 @@
|
|||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <1>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@2 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <2>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@3 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <3>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@4 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <4>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@5 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <5>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
model = "tms320c6472";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
core_pic: interrupt-controller {
|
||||||
|
compatible = "ti,c64x+core-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
compatible = "ti,c64x+megamod-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
reg = <0x1800000 0x1000>;
|
||||||
|
interrupt-parent = <&core_pic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cache-controller@1840000 {
|
||||||
|
compatible = "ti,c64x+cache";
|
||||||
|
reg = <0x01840000 0x8400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer0: timer@25e0000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x01 >;
|
||||||
|
reg = <0x25e0000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer1: timer@25f0000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x02 >;
|
||||||
|
reg = <0x25f0000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer2: timer@2600000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x04 >;
|
||||||
|
reg = <0x2600000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3: timer@2610000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x08 >;
|
||||||
|
reg = <0x2610000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer4: timer@2620000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x10 >;
|
||||||
|
reg = <0x2620000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer5: timer@2630000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x20 >;
|
||||||
|
reg = <0x2630000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@29a0000 {
|
||||||
|
compatible = "ti,c6472-pll", "ti,c64x+pll";
|
||||||
|
reg = <0x029a0000 0x200>;
|
||||||
|
ti,c64x+pll-bypass-delay = <200>;
|
||||||
|
ti,c64x+pll-reset-delay = <12000>;
|
||||||
|
ti,c64x+pll-lock-delay = <80000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
device-state-controller@2a80000 {
|
||||||
|
compatible = "ti,c64x+dscr";
|
||||||
|
reg = <0x02a80000 0x1000>;
|
||||||
|
|
||||||
|
ti,dscr-devstat = <0>;
|
||||||
|
ti,dscr-silicon-rev = <0x70c 16 0xff>;
|
||||||
|
|
||||||
|
ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
|
||||||
|
0x704 5 6 0 0>;
|
||||||
|
|
||||||
|
ti,dscr-rmii-resets = <0x208 1
|
||||||
|
0x20c 1>;
|
||||||
|
|
||||||
|
ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
|
||||||
|
0x40c 0x420 0xbea7
|
||||||
|
0x41c 0x420 0xbea7>;
|
||||||
|
|
||||||
|
ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
|
||||||
|
|
||||||
|
ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,89 @@
|
|||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <1>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
cpu@2 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <2>;
|
||||||
|
model = "ti,c64x+";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
model = "tms320c6474";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
core_pic: interrupt-controller {
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
compatible = "ti,c64x+core-pic";
|
||||||
|
};
|
||||||
|
|
||||||
|
megamod_pic: interrupt-controller@1800000 {
|
||||||
|
compatible = "ti,c64x+megamod-pic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
reg = <0x1800000 0x1000>;
|
||||||
|
interrupt-parent = <&core_pic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cache-controller@1840000 {
|
||||||
|
compatible = "ti,c64x+cache";
|
||||||
|
reg = <0x01840000 0x8400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3: timer@2940000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x04 >;
|
||||||
|
reg = <0x2940000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer4: timer@2950000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x02 >;
|
||||||
|
reg = <0x2950000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer5: timer@2960000 {
|
||||||
|
compatible = "ti,c64x+timer64";
|
||||||
|
ti,core-mask = < 0x01 >;
|
||||||
|
reg = <0x2960000 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
device-state-controller@2880800 {
|
||||||
|
compatible = "ti,c64x+dscr";
|
||||||
|
reg = <0x02880800 0x400>;
|
||||||
|
|
||||||
|
ti,dscr-devstat = <0x004>;
|
||||||
|
ti,dscr-silicon-rev = <0x014 28 0xf>;
|
||||||
|
ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
|
||||||
|
0x38 0 0 1 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock-controller@29a0000 {
|
||||||
|
compatible = "ti,c6474-pll", "ti,c64x+pll";
|
||||||
|
reg = <0x029a0000 0x200>;
|
||||||
|
ti,c64x+pll-bypass-delay = <120>;
|
||||||
|
ti,c64x+pll-reset-delay = <30000>;
|
||||||
|
ti,c64x+pll-lock-delay = <60000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@@ -0,0 +1,2 @@
|
|||||||
|
.section __fdt_blob,"a"
|
||||||
|
.incbin "arch/c6x/boot/builtin.dtb"
|
||||||
@@ -0,0 +1,44 @@
|
|||||||
|
CONFIG_SOC_TMS320C6455=y
|
||||||
|
CONFIG_EXPERIMENTAL=y
|
||||||
|
# CONFIG_LOCALVERSION_AUTO is not set
|
||||||
|
CONFIG_SYSVIPC=y
|
||||||
|
CONFIG_SPARSE_IRQ=y
|
||||||
|
CONFIG_LOG_BUF_SHIFT=14
|
||||||
|
CONFIG_NAMESPACES=y
|
||||||
|
# CONFIG_UTS_NS is not set
|
||||||
|
# CONFIG_USER_NS is not set
|
||||||
|
# CONFIG_PID_NS is not set
|
||||||
|
CONFIG_BLK_DEV_INITRD=y
|
||||||
|
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||||
|
CONFIG_EXPERT=y
|
||||||
|
# CONFIG_FUTEX is not set
|
||||||
|
# CONFIG_SLUB_DEBUG is not set
|
||||||
|
CONFIG_MODULES=y
|
||||||
|
CONFIG_MODULE_FORCE_LOAD=y
|
||||||
|
CONFIG_MODULE_UNLOAD=y
|
||||||
|
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||||
|
CONFIG_CMDLINE_BOOL=y
|
||||||
|
CONFIG_CMDLINE=""
|
||||||
|
CONFIG_NO_HZ=y
|
||||||
|
CONFIG_HIGH_RES_TIMERS=y
|
||||||
|
CONFIG_BLK_DEV_LOOP=y
|
||||||
|
CONFIG_BLK_DEV_RAM=y
|
||||||
|
CONFIG_BLK_DEV_RAM_COUNT=2
|
||||||
|
CONFIG_BLK_DEV_RAM_SIZE=17000
|
||||||
|
CONFIG_MISC_DEVICES=y
|
||||||
|
# CONFIG_INPUT is not set
|
||||||
|
# CONFIG_SERIO is not set
|
||||||
|
# CONFIG_VT is not set
|
||||||
|
# CONFIG_HW_RANDOM is not set
|
||||||
|
# CONFIG_HWMON is not set
|
||||||
|
# CONFIG_USB_SUPPORT is not set
|
||||||
|
# CONFIG_IOMMU_SUPPORT is not set
|
||||||
|
# CONFIG_MISC_FILESYSTEMS is not set
|
||||||
|
CONFIG_CRC16=y
|
||||||
|
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||||
|
# CONFIG_SCHED_DEBUG is not set
|
||||||
|
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_MTD_CFI=y
|
||||||
|
CONFIG_MTD_CFI_AMDSTD=y
|
||||||
|
CONFIG_MTD_PHYSMAP_OF=y
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user