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ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)

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The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Philipp Zabel
2013-03-28 17:35:19 +01:00
committed by Shawn Guo
parent 7006ba24c2
commit 02985b9463
3 changed files with 115 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/mach-imx/src.c
+65
View File
@@ -14,16 +14,72 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/reset-controller.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#define SRC_SCR 0x000
#define SRC_GPR1 0x020
#define BP_SRC_SCR_WARM_RESET_ENABLE 0
#define BP_SRC_SCR_SW_GPU_RST 1
#define BP_SRC_SCR_SW_VPU_RST 2
#define BP_SRC_SCR_SW_IPU1_RST 3
#define BP_SRC_SCR_SW_OPEN_VG_RST 4
#define BP_SRC_SCR_SW_IPU2_RST 12
#define BP_SRC_SCR_CORE1_RST 14
#define BP_SRC_SCR_CORE1_ENABLE 22
static void __iomem *src_base;
static DEFINE_SPINLOCK(scr_lock);
static const int sw_reset_bits[5] = {
BP_SRC_SCR_SW_GPU_RST,
BP_SRC_SCR_SW_VPU_RST,
BP_SRC_SCR_SW_IPU1_RST,
BP_SRC_SCR_SW_OPEN_VG_RST,
BP_SRC_SCR_SW_IPU2_RST
};
static int imx_src_reset_module(struct reset_controller_dev *rcdev,
unsigned long sw_reset_idx)
{
unsigned long timeout;
unsigned long flags;
int bit;
u32 val;
if (!src_base)
return -ENODEV;
if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
return -EINVAL;
bit = 1 << sw_reset_bits[sw_reset_idx];
spin_lock_irqsave(&scr_lock, flags);
val = readl_relaxed(src_base + SRC_SCR);
val |= bit;
writel_relaxed(val, src_base + SRC_SCR);
spin_unlock_irqrestore(&scr_lock, flags);
timeout = jiffies + msecs_to_jiffies(1000);
while (readl(src_base + SRC_SCR) & bit) {
if (time_after(jiffies, timeout))
return -ETIME;
cpu_relax();
}
return 0;
}
static struct reset_control_ops imx_src_ops = {
.reset = imx_src_reset_module,
};
static struct reset_controller_dev imx_reset_controller = {
.ops = &imx_src_ops,
.nr_resets = ARRAY_SIZE(sw_reset_bits),
};
void imx_enable_cpu(int cpu, bool enable)
{
@@ -31,9 +87,11 @@ void imx_enable_cpu(int cpu, bool enable)
cpu = cpu_logical_map(cpu);
mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
spin_lock(&scr_lock);
val = readl_relaxed(src_base + SRC_SCR);
val = enable ? val | mask : val & ~mask;
writel_relaxed(val, src_base + SRC_SCR);
spin_unlock(&scr_lock);
}
void imx_set_cpu_jump(int cpu, void *jump_addr)
@@ -60,9 +118,11 @@ void imx_src_prepare_restart(void)
u32 val;
/* clear enable bits of secondary cores */
spin_lock(&scr_lock);
val = readl_relaxed(src_base + SRC_SCR);
val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
writel_relaxed(val, src_base + SRC_SCR);
spin_unlock(&scr_lock);
/* clear persistent entry register of primary core */
writel_relaxed(0, src_base + SRC_GPR1);
@@ -77,11 +137,16 @@ void __init imx_src_init(void)
src_base = of_iomap(np, 0);
WARN_ON(!src_base);
imx_reset_controller.of_node = np;
reset_controller_register(&imx_reset_controller);
/*
* force warm reset sources to generate cold reset
* for a more reliable restart
*/
spin_lock(&scr_lock);
val = readl_relaxed(src_base + SRC_SCR);
val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
writel_relaxed(val, src_base + SRC_SCR);
spin_unlock(&scr_lock);
}