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serial: sh-sci: Move SCSCR_INIT in to platform data.

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This moves all of the SCSCR_INIT definitions in to the platform data,
for future consolidation.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
2009-06-24 17:53:33 +09:00
parent bb38c222e0
commit 00b9de9c24
27 changed files with 140 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/sh/kernel/cpu/sh2/setup-sh7619.c
+3
View File
@@ -63,16 +63,19 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xf8400000, .mapbase = 0xf8400000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 88, 88, 88, 88 }, .irqs = { 88, 88, 88, 88 },
}, { }, {
.mapbase = 0xf8410000, .mapbase = 0xf8410000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 92, 92, 92, 92 }, .irqs = { 92, 92, 92, 92 },
}, { }, {
.mapbase = 0xf8420000, .mapbase = 0xf8420000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 96, 96, 96, 96 }, .irqs = { 96, 96, 96, 96 },
}, { }, {
arch/sh/kernel/cpu/sh2a/setup-mxg.c
+1
View File
@@ -211,6 +211,7 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xff804000, .mapbase = 0xff804000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 220, 220, 220, 220 }, .irqs = { 220, 220, 220, 220 },
}, { }, {
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+8
View File
@@ -181,41 +181,49 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xfffe8000, .mapbase = 0xfffe8000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 180, 180, 180, 180 } .irqs = { 180, 180, 180, 180 }
}, { }, {
.mapbase = 0xfffe8800, .mapbase = 0xfffe8800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 184, 184, 184, 184 } .irqs = { 184, 184, 184, 184 }
}, { }, {
.mapbase = 0xfffe9000, .mapbase = 0xfffe9000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 188, 188, 188, 188 } .irqs = { 188, 188, 188, 188 }
}, { }, {
.mapbase = 0xfffe9800, .mapbase = 0xfffe9800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 192, 192, 192, 192 } .irqs = { 192, 192, 192, 192 }
}, { }, {
.mapbase = 0xfffea000, .mapbase = 0xfffea000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 196, 196, 196, 196 } .irqs = { 196, 196, 196, 196 }
}, { }, {
.mapbase = 0xfffea800, .mapbase = 0xfffea800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 200, 200, 200, 200 } .irqs = { 200, 200, 200, 200 }
}, { }, {
.mapbase = 0xfffeb000, .mapbase = 0xfffeb000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 204, 204, 204, 204 } .irqs = { 204, 204, 204, 204 }
}, { }, {
.mapbase = 0xfffeb800, .mapbase = 0xfffeb800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 208, 208, 208, 208 } .irqs = { 208, 208, 208, 208 }
}, { }, {
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+4
View File
@@ -177,21 +177,25 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xfffe8000, .mapbase = 0xfffe8000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 192, 192, 192, 192 }, .irqs = { 192, 192, 192, 192 },
}, { }, {
.mapbase = 0xfffe8800, .mapbase = 0xfffe8800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 196, 196, 196, 196 }, .irqs = { 196, 196, 196, 196 },
}, { }, {
.mapbase = 0xfffe9000, .mapbase = 0xfffe9000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 200, 200, 200, 200 }, .irqs = { 200, 200, 200, 200 },
}, { }, {
.mapbase = 0xfffe9800, .mapbase = 0xfffe9800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 204, 204, 204, 204 }, .irqs = { 204, 204, 204, 204 },
}, { }, {
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+4
View File
@@ -137,21 +137,25 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xfffe8000, .mapbase = 0xfffe8000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 240, 240, 240, 240 }, .irqs = { 240, 240, 240, 240 },
}, { }, {
.mapbase = 0xfffe8800, .mapbase = 0xfffe8800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 244, 244, 244, 244 }, .irqs = { 244, 244, 244, 244 },
}, { }, {
.mapbase = 0xfffe9000, .mapbase = 0xfffe9000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 248, 248, 248, 248 }, .irqs = { 248, 248, 248, 248 },
}, { }, {
.mapbase = 0xfffe9800, .mapbase = 0xfffe9800,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 252, 252, 252, 252 }, .irqs = { 252, 252, 252, 252 },
}, { }, {
arch/sh/kernel/cpu/sh3/setup-sh7705.c
+3
View File
@@ -71,11 +71,14 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xa4410000, .mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 56, 56, 56 }, .irqs = { 56, 56, 56 },
}, { }, {
.mapbase = 0xa4400000, .mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 52, 52, 52 }, .irqs = { 52, 52, 52 },
}, { }, {
arch/sh/kernel/cpu/sh3/setup-sh770x.c
+3
View File
@@ -110,6 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xfffffe80, .mapbase = 0xfffffe80,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.type = PORT_SCI, .type = PORT_SCI,
.irqs = { 23, 23, 23, 0 }, .irqs = { 23, 23, 23, 0 },
}, },
@@ -119,6 +120,7 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xa4000150, .mapbase = 0xa4000150,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 }, .irqs = { 56, 56, 56, 56 },
}, },
@@ -128,6 +130,7 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xa4000140, .mapbase = 0xa4000140,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.type = PORT_IRDA, .type = PORT_IRDA,
.irqs = { 52, 52, 52, 52 }, .irqs = { 52, 52, 52, 52 },
}, },
arch/sh/kernel/cpu/sh3/setup-sh7710.c
+4
View File
@@ -100,11 +100,15 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xa4400000, .mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 52, 52, 52, 52 }, .irqs = { 52, 52, 52, 52 },
}, { }, {
.mapbase = 0xa4410000, .mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 }, .irqs = { 56, 56, 56, 56 },
}, { }, {
arch/sh/kernel/cpu/sh3/setup-sh7720.c
+3 -2
View File
@@ -1,5 +1,5 @@
/* /*
* SH7720 Setup * Setup code for SH7720, SH7721.
* *
* Copyright (C) 2007 Markus Brunner, Mark Jonas * Copyright (C) 2007 Markus Brunner, Mark Jonas
* Copyright (C) 2009 Paul Mundt * Copyright (C) 2009 Paul Mundt
@@ -52,15 +52,16 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xa4430000, .mapbase = 0xa4430000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
}, { }, {
.mapbase = 0xa4438000, .mapbase = 0xa4438000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
}, { }, {
.flags = 0, .flags = 0,
} }
}; };
arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+1
View File
@@ -19,6 +19,7 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe80000, .mapbase = 0xffe80000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 40, 41, 43, 42 }, .irqs = { 40, 41, 43, 42 },
}, { }, {
arch/sh/kernel/cpu/sh4/setup-sh7750.c
+30 -18
View File
@@ -14,6 +14,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/sh_timer.h> #include <linux/sh_timer.h>
#include <linux/serial_sci.h> #include <linux/serial_sci.h>
#include <asm/machtypes.h>
static struct resource rtc_resources[] = { static struct resource rtc_resources[] = {
[0] = { [0] = {
@@ -35,32 +36,36 @@ static struct platform_device rtc_device = {
.resource = rtc_resources, .resource = rtc_resources,
}; };
static struct plat_sci_port sci_platform_data[] = { static struct plat_sci_port sci_platform_data = {
{ .mapbase = 0xffe00000,
#ifndef CONFIG_SH_RTS7751R2D .flags = UPF_BOOT_AUTOCONF,
.mapbase = 0xffe00000, .type = PORT_SCI,
.flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE,
.type = PORT_SCI, .irqs = { 23, 23, 23, 0 },
.irqs = { 23, 23, 23, 0 },
}, {
#endif
.mapbase = 0xffe80000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 },
}, {
.flags = 0,
}
}; };
static struct platform_device sci_device = { static struct platform_device sci_device = {
.name = "sh-sci", .name = "sh-sci",
.id = -1,
.dev = { .dev = {
.platform_data = sci_platform_data, .platform_data = sci_platform_data,
}, },
}; };
static struct plat_sci_port scif_platform_data = {
.mapbase = 0xffe80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
.type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 },
};
static struct platform_device scif_device = {
.name = "sh-sci",
.dev = {
.platform_data = scif_platform_data,
},
};
static struct sh_timer_config tmu0_platform_data = { static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0", .name = "TMU0",
.channel_offset = 0x04, .channel_offset = 0x04,
@@ -222,7 +227,6 @@ static struct platform_device tmu4_device = {
static struct platform_device *sh7750_devices[] __initdata = { static struct platform_device *sh7750_devices[] __initdata = {
&rtc_device, &rtc_device,
&sci_device,
&tmu0_device, &tmu0_device,
&tmu1_device, &tmu1_device,
&tmu2_device, &tmu2_device,
@@ -236,6 +240,14 @@ static struct platform_device *sh7750_devices[] __initdata = {
static int __init sh7750_devices_setup(void) static int __init sh7750_devices_setup(void)
{ {
if (mach_is_rts7751r2d()) {
scif_platform_data.scscr |= SCSCR_CKE1;
platform_register_device(&scif_device);
} else {
platform_register_device(&sci_device);
platform_register_device(&scif_device);
}
return platform_add_devices(sh7750_devices, return platform_add_devices(sh7750_devices,
ARRAY_SIZE(sh7750_devices)); ARRAY_SIZE(sh7750_devices));
} }
arch/sh/kernel/cpu/sh4/setup-sh7760.c
+4
View File
@@ -130,21 +130,25 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xfe600000, .mapbase = 0xfe600000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 52, 53, 55, 54 }, .irqs = { 52, 53, 55, 54 },
}, { }, {
.mapbase = 0xfe610000, .mapbase = 0xfe610000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 72, 73, 75, 74 }, .irqs = { 72, 73, 75, 74 },
}, { }, {
.mapbase = 0xfe620000, .mapbase = 0xfe620000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 76, 77, 79, 78 }, .irqs = { 76, 77, 79, 78 },
}, { }, {
.mapbase = 0xfe480000, .mapbase = 0xfe480000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCI, .type = PORT_SCI,
.irqs = { 80, 81, 82, 0 }, .irqs = { 80, 81, 82, 0 },
}, { }, {
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+4
View File
@@ -269,24 +269,28 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0", .clk = "scif0",
}, { }, {
.mapbase = 0xffe10000, .mapbase = 0xffe10000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1", .clk = "scif1",
}, { }, {
.mapbase = 0xffe20000, .mapbase = 0xffe20000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2", .clk = "scif2",
}, { }, {
.mapbase = 0xffe30000, .mapbase = 0xffe30000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 83, 83, 83, 83 }, .irqs = { 83, 83, 83, 83 },
.clk = "scif3", .clk = "scif3",
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+1
View File
@@ -280,6 +280,7 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0", .clk = "scif0",
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+6 -6
View File
@@ -305,25 +305,25 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0", .clk = "scif0",
}, }, {
{
.mapbase = 0xffe10000, .mapbase = 0xffe10000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1", .clk = "scif1",
}, }, {
{
.mapbase = 0xffe20000, .mapbase = 0xffe20000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2", .clk = "scif2",
}, }, {
{
.flags = 0, .flags = 0,
} }
}; };
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+6
View File
@@ -321,36 +321,42 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0", .clk = "scif0",
},{ },{
.mapbase = 0xffe10000, .mapbase = 0xffe10000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1", .clk = "scif1",
},{ },{
.mapbase = 0xffe20000, .mapbase = 0xffe20000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2", .clk = "scif2",
},{ },{
.mapbase = 0xa4e30000, .mapbase = 0xa4e30000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 56, 56, 56, 56 }, .irqs = { 56, 56, 56, 56 },
.clk = "scif3", .clk = "scif3",
},{ },{
.mapbase = 0xa4e40000, .mapbase = 0xa4e40000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 88, 88, 88, 88 }, .irqs = { 88, 88, 88, 88 },
.clk = "scif4", .clk = "scif4",
},{ },{
.mapbase = 0xa4e50000, .mapbase = 0xa4e50000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 109, 109, 109, 109 }, .irqs = { 109, 109, 109, 109 },
.clk = "scif5", .clk = "scif5",
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+6
View File
@@ -28,36 +28,42 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0", .clk = "scif0",
}, { }, {
.mapbase = 0xffe10000, .mapbase = 0xffe10000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1", .clk = "scif1",
}, { }, {
.mapbase = 0xffe20000, .mapbase = 0xffe20000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2", .clk = "scif2",
}, { }, {
.mapbase = 0xa4e30000, .mapbase = 0xa4e30000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 56, 56, 56, 56 }, .irqs = { 56, 56, 56, 56 },
.clk = "scif3", .clk = "scif3",
}, { }, {
.mapbase = 0xa4e40000, .mapbase = 0xa4e40000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 88, 88, 88, 88 }, .irqs = { 88, 88, 88, 88 },
.clk = "scif4", .clk = "scif4",
}, { }, {
.mapbase = 0xa4e50000, .mapbase = 0xa4e50000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 109, 109, 109, 109 }, .irqs = { 109, 109, 109, 109 },
.clk = "scif5", .clk = "scif5",
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+3
View File
@@ -40,16 +40,19 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 }, .irqs = { 40, 40, 40, 40 },
}, { }, {
.mapbase = 0xffe08000, .mapbase = 0xffe08000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 76, 76, 76, 76 }, .irqs = { 76, 76, 76, 76 },
}, { }, {
.mapbase = 0xffe10000, .mapbase = 0xffe10000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 104, 104, 104, 104 }, .irqs = { 104, 104, 104, 104 },
}, { }, {
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+10
View File
@@ -18,51 +18,61 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xff923000, .mapbase = 0xff923000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 61, 61, 61, 61 }, .irqs = { 61, 61, 61, 61 },
}, { }, {
.mapbase = 0xff924000, .mapbase = 0xff924000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 62, 62, 62, 62 }, .irqs = { 62, 62, 62, 62 },
}, { }, {
.mapbase = 0xff925000, .mapbase = 0xff925000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 63, 63, 63, 63 }, .irqs = { 63, 63, 63, 63 },
}, { }, {
.mapbase = 0xff926000, .mapbase = 0xff926000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 64, 64, 64, 64 }, .irqs = { 64, 64, 64, 64 },
}, { }, {
.mapbase = 0xff927000, .mapbase = 0xff927000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 65, 65, 65, 65 }, .irqs = { 65, 65, 65, 65 },
}, { }, {
.mapbase = 0xff928000, .mapbase = 0xff928000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 66, 66, 66, 66 }, .irqs = { 66, 66, 66, 66 },
}, { }, {
.mapbase = 0xff929000, .mapbase = 0xff929000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 67, 67, 67, 67 }, .irqs = { 67, 67, 67, 67 },
}, { }, {
.mapbase = 0xff92a000, .mapbase = 0xff92a000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 68, 68, 68, 68 }, .irqs = { 68, 68, 68, 68 },
}, { }, {
.mapbase = 0xff92b000, .mapbase = 0xff92b000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 69, 69, 69, 69 }, .irqs = { 69, 69, 69, 69 },
}, { }, {
.mapbase = 0xff92c000, .mapbase = 0xff92c000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 70, 70, 70, 70 }, .irqs = { 70, 70, 70, 70 },
}, { }, {
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+2
View File
@@ -220,11 +220,13 @@ static struct plat_sci_port sci_platform_data[] = {
{ {
.mapbase = 0xffe00000, .mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 }, .irqs = { 40, 40, 40, 40 },
}, { }, {
.mapbase = 0xffe10000, .mapbase = 0xffe10000,
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 76, 76, 76, 76 }, .irqs = { 76, 76, 76, 76 },
}, { }, {

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