* Add RISC-V performance CSR support
* RISC-V Read_CSR_64: fix rv32 version
* RISC-V improve CSR support
Add sub-program to swap, set bits, clear bits, etc.
Instantiate sub-programs for all machine CSRs.
* Olimex STM32-H405 board support
* Add STM32-H405 to build_all_examples.py, fix for style checks
* Use stm32f4 runtime for STM32-H405 board
* Add STM32_H405 to board_projects_generator.py
startup-gen is a tool that generates crt0 and linker script from a
device configuration (CPU name, memory layout). The tool only works for
ZFP run-times right now.
This patch also switches the HiFive1 support to use startup-gen.