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35 Commits

Author SHA1 Message Date
Fabien Chouteau
c9290bc39d Add RISC-V performance CSR support (#363) 
* Add RISC-V performance CSR support

* RISC-V Read_CSR_64: fix rv32 version

* RISC-V improve CSR support

Add sub-program to swap, set bits, clear bits, etc.
Instantiate sub-programs for all machine CSRs.
 2020-09-15 18:08:30 +02:00
Fabien Chouteau
a61be055b9 RISC-V/SiFive: Add uart0 driver 2019-09-06 12:35:02 +02:00
Fabien Chouteau
8677f892a9 Add SiFive Unleased definition including a new device definition system 
In the future, this device definition system could be combined with a
device tree parser.
 2019-09-06 12:35:02 +02:00
Fabien Chouteau
7f756adc0e Add reusable SiFive drivers 
This drivers will work on multiple instances of SiFive SOCs.
 2019-09-06 12:35:02 +02:00
Fabien Chouteau
ddab92871d Merge pull request #265 from AdaCore/gpio_capabilities 
[RFC] HAL.GPIO: Switch to a capability system
 2018-07-13 18:35:46 +02:00
Fabien Chouteau
cbdffd1b9c FE310: Remove useless with 2018-07-11 19:56:51 +02:00
Fabien Chouteau
4d32971732 HAL.GPIO: Switch to a capability system 
Instead of returning False when a configuration is not supported, users
can call a function beforehand to know if it is supported. The
capability is also now a precondition of the setup procedures.
 2018-07-11 18:46:16 +02:00
elbric0
daf9c63736 Use Delay_Us for all the FE310 Delay_* procedures 2018-05-29 16:02:53 -04:00
elbric0
2639968068 Simplify the functions reading the FE310 Machine Timer and RTC 2018-05-29 16:02:31 -04:00
elbric0
e21a77bf82 Cosmetic changes 
Following the comments made by Fabien Chouteau.
 2018-05-29 16:02:24 -04:00
elbric0
a4118b227c Update the fe310_svd-spi.ads file with the one generated by the latest 
version of svd2ada.
 2018-05-08 08:07:03 -04:00
elbric0
2b32a3cb48 - Add support for the FE310 PLL 
- Move the sub-package time from HiFive1 to FE310
 2018-05-08 08:07:03 -04:00
elbric0
d13b080147 FE310: Add basic support for clock configuration. 2018-05-08 08:07:03 -04:00
elbric0
f368b799f0 - Delay procedures using the Machine Timer 
- Different base addresses for the AON domain modules
- Fix a typo in fe310_svd-pwm.ads
 2018-05-08 08:07:03 -04:00
elbric0
db78133955 Add FE310 RTC support. 2018-05-08 08:07:03 -04:00
Fabien Chouteau
571f0d2f1a Remove unused project files 2018-04-27 21:16:41 +02:00
elbric0
70e3cc8988 Bring back the IO Functions definitions. 2018-03-06 22:48:27 -05:00
Fabien Chouteau
f07684edaf FE310: Add support of PWM 2018-01-19 19:11:30 +01:00
Fabien Chouteau
54a7de52db FE310_SVD: Update generated code with better description of PWM 2018-01-19 19:11:30 +01:00
Fabien Chouteau
0c35957fa0 FE310.GPIO: Add invert control sub-programs 2018-01-19 19:10:36 +01:00
Fabien Chouteau
3a7945c20a Use new GPRbuild attribute: Create_Missing_Dirs 
And remove now useless .gitignore files and empty directories.
 2017-06-27 15:58:10 +02:00
Jerome Lambourg
b4acbb9ad9 Further refactor the board projects. 
This commit in particular removes the need for aggregate projects.
 2017-06-26 18:18:59 +02:00
Jerome Lambourg
5856f7923c Regenerate the SVD files with latest svd2ada version. 
This also fixes missing fields in the RCC peripherals for the stm32f7
 2017-03-28 14:44:02 +02:00
Fabien Chouteau
bd516c1e89 FE310.UART: Fix compile error 2017-03-10 19:20:04 +01:00
Fabien Chouteau
632b449d1d HAL types: Revert UInt1 to Bit 2017-02-15 19:04:27 +01:00